R8C/38T-A Group
21. Clock Synchronous Serial Interface
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 464 of 730
Aug 05, 2011
21.2.3
SI Transmit Data Register (SITDR)
Note:
1. A data transfer length of 9 bits or more (b8 to b15) is only used with the SSU function. When setting the SSU data
transfer length to 9 bits or more using the SSBR register, access the SITDR register in 16-bit units.
When using 8-bit access, the transmit operation will not be started even if the higher byte (b15 to b8) is
accessed. When the lower byte (b7 to b0) is accessed, TDRE is negated and the transmit operation starts.
21.2.4
SI Receive Data Register (SIRDR)
Notes:
1. When the ORER_AL bit in the SISR register is set to 1 (overrun error), the SIRDR register retains the data
received before the overrun error occurred. The receive data (data in the SISDR register) when an overrun error
occurs is discarded.
2. A SSU data transfer length of 9 bits or more (b8 to b15) is only used with the SSU function. When setting the
SSU data transfer length to 9 bits or more using the SSBR register, access the SIRDR register in 16-bit units.
When the SIRDR register is accessed in 8-bit units, the RDRF bit in the SISR register is also set to 0 (no data in
the SIRDR register).
3. Read the SIRDR register when the RDRF bit is 1 (data present in the SIRDR register).
Address 000E2h (SITDR_0)
Bit
b7b6
b5b4b3
b2b1b0
Symbol
————
———
—
After Reset
1
111
1111
Bit
b15
b14
b13
b12
b11
b10
b9
b8
Symbol
————
———
—
After Reset
1
111
1111
Bit
Function
R/W
b15 to b0 Store the transmit data.
(1)When it is detected that the SISDR register is empty, the transmit data stored in this register is
transferred to the SISDR register and transmission is started.
If the next transmit data has been written to the SITDR register during the data transmission from
the SISDR register, the data can be transmitted consecutively.
When the MLS bit in the SIMR1 register is 1 (data transfer with LSB first), the data with inverted
MSB and LSB is read after writing to the SITDR register.
R/W
Address 000E4h (SIRDR_0)
Bit
b7b6
b5b4b3
b2b1b0
Symbol
————
———
—
After Reset
1
111
1111
Bit
b15
b14
b13
b12
b11
b10
b9
b8
Symbol
————
———
—
After Reset
1
111
1111
Bit
Function
R/W
When 1 byte of data has been received by the SISDR register, the receive data is transferred to
the SIRDR register and the receive operation completes. At this time, the next receive operation is
enabled.
Continuous reception is possible using registers SISDR and SIRDR.
R