R8C/38T-A Group
9. Clock Generation Circuit
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 103 of 730
Aug 05, 2011
9.7
Oscillation Stop Detection Function
The oscillation stop detection function is used to detect whether the XIN clock oscillation is stopped.
The oscillation stop detection function can be enabled or disabled with the OCD0 bit in the OCD register.
When the XIN clock is the CPU clock source and bits OCD1 and OCD0 are 11b, if the XIN clock is stopped, the
states will change as follows:
Bits CM42 to CM40 in CM4 register = 001b (fLOCO)
CM14 bit in CM1 register = 0 (low-speed on-chip oscillator on).
An oscillation stop detection interrupt is generated
9.7.1
How to Use Oscillation Stop Detection Function
The oscillation stop detection interrupt shares a vector with the watchdog timer, voltage monitor 1, and
voltage monitor 2 interrupts. To use both the oscillation stop detection and watchdog timer interrupts, the
interrupt source needs to be determined.
When the XIN clock reoscillates after oscillation is stopped, switch the XIN clock to the clock source for the
CPU clock and the peripheral functions by a program.
When entering wait mode while using the oscillation stop detection function, set the CM02 bit in the CM0
register to 0 (peripheral function clock does not stop in wait mode).
Since the oscillation stop detection function is a function for cases where the XIN clock is stopped by an
external cause, set bits OCD1 and OCD0 to 00b to stop or oscillate the XIN clock by a program (to select stop
mode or change the CM05 bit in the CM05 register).
This function cannot be used when the XIN clock frequency is below 2 MHz. In this case, set bits OCD1 and
OCD0 to 00b.
To use the low-speed on-chip oscillator clock for the clock source for the CPU clock and the peripheral
functions after oscillation stop is detected, set the OCD6 bit in the OCD register to 0 (low-speed on-chip
oscillator selected) before setting bits OCD1 and OCD0 to 11b.
To use the high-speed on-chip oscillator clock for the clock source for the CPU clock and the peripheral
functions after oscillation stop is detected, set the FRA00 bit in the FRA0 register to 1 (high-speed on-chip
oscillator on) and the OCD6 bit to 1 (high-speed on-chip oscillator selected) before setting bits OCD1 and
OCD0 to 11b.
Table 9.6
Oscillation Stop Detection Function Specifications
Item
Specification
Clock frequency range for oscillation
stop detection
f(XIN)
2 MHz
Condition for enabling the oscillation
stop detection function
Set bits OCD1 and OCD0 in the OCD register to 11b.
Operation at oscillation stop detection
An oscillation stop detection interrupt is generated.