R8C/38T-A Group
20. Serial Interface (UART2)
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 439 of 730
Aug 05, 2011
Figure 20.18
Timing of SCL2 Pin Low Output Hold Function 1
(2) SCL2 Pin Low Output Hold Function 2
UART2 requires at maximum 1.5 cycles of the transfer clock after transmit data is written to the transmit
buffer until the transfer clock (SCL) is transmitted. In addition, because the SCL synchronization function
of UART2 is enabled from the first bit of SCL transmission, if another device transmits a first bit in the
period from when the start condition is generated until the SCL synchronization function is enabled, the bit
may be shifted. Therefore, SCL2 pin low output hold function 2 of UART2 was created to disable clock
transmission from other devices after the start condition is transmitted. By using this function, a low level
is output to the SCL2 pin at the same time that data is written to the transmit buffer, and other devices can
be put into a wait state. This function is enabled by setting the SWC2 bit to 1, and disabled by setting it to
0. This function should only be used when the MCU is being used as a master.
Figure 20.19 shows the
Figure 20.19
Timing of SCL2 Pin Low Output Hold Function 2
(Address comparison
processing)
Set the SWC bit to 1
1st bit
Transmit SCL
SWC
2nd bit
8th bit
9th bit
The SCL2 pin is held low here
(When the IICM bit is 1, a UART2
receive interrupt is generated)
Setting the SWC bit to 0
releases the SCL2 pin
from low output
SCL synchronization function enabled
Maximum 1.5 cycles
When not using SCL2 pin output function (SWC2 = 0)
SCL of other
device
SDA2
Transmit SCL
SWC2
0
1st bit
2nd bit
3rd bit
1st bit
(N
ote
1)
SCL synchronization function enabled
When using SCL2 pin output function (SWC2 = 1)
SCL of other
device
SDA2
Transmit SCL
SWC2
1st bit
2nd bit
Secure over 1.5 cycles
of SCL
Note:
1. Bit shifted.
Completion of writing transmit data