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| 型号： | M-ORSO82G51BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 1/123页 |
| 文件大小： | 2207K |
| 代理商： | M-ORSO82G51BM680-DB |
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www.latticesemi.com
1
orso82g5_01
ORCA ORSO82G5
1.0 - 2.7 Gbps SONET Backplane Interface FPSC
October 2002
Preliminary Data Sheet
Introduction
Lattice has extended its family of high-speed serial backplane devices with the ORSO82G5 device. Built on the
Series 4 recongurable embedded System-on-a-Chip (SoC) architecture, the ORSO82G5 is a high-speed trans-
ceiver with an aggregate bandwidth of over 20 Gbits/s that is targeted towards users needing high-speed back-
plane interfaces for SONET and other non-SONET applications. The ORSO82G5 has 8 channels of integrated 1.0-
2.7G SERDES channels with built-in Clock and Data Recovery (CDR), along with more than 400K usable FPGA
system gates. The CDR circuitry is a macrocell available from Lattice's smart silicon macro library and has already
been implemented in numerous applications, including ASICs, standard products, and FPSCs, to create interfaces
for STS-48/STM-16 and STS-192/STM-64 SONET/SDH applications. With the addition of protocol and access
logic such as protocol-independent framers, Asynchronous Transfer Mode (ATM) framers, Packet-over-SONET
(PoS) interfaces, and framers for HDLC for Internet Protocol (IP), designers can build a congurable interface
retaining proven backplane driver/receiver technology. Designers can also use the device to drive high-speed data
transfer across buses within a system that are not SONET/SDH based. The ORSO82G5 can also be used to pro-
vide a full 10 Gbits/s backplane data connection with protection between a line card and switch fabric.
The ORSO82G5 supports a clockless high-speed interface for interdevice communication on a board or across a
backplane. The built-in clock recovery of the ORSO82G5 allows for higher system performance, easier-to-design
clock domains in a multiboard system and fewer signals on the backplane. Network designers will benet from
using the backplane transceiver as a network termination device. A sister device, called the ORT82G5, supports
8B/10B encoding/decoding and link state machines for 10 Gbit Ethernet (XAUI) and Fiber Channel. The
ORSO82G5 performs SONET data scrambling/descrambling, streamlined SONET framing, limited Transport Over-
Head (TOH) handling, plus the programmable logic to terminate the network into proprietary systems. The cell pro-
cessing feature in the ORSO82G5 makes it ideal for interfacing devices with any proprietary data format across a
high-speed backplane. For non-SONET applications, all SONET functionality is hidden from the user and no prior
networking knowledge is required. The ORSO82G5 is completely pin-compatible with the ORT82G5 device.
Table 1. ORCA ORSO82G5 Family—Available FPGA Logic
1. The embedded core, Embedded System Bus, FPGA interface and MPI are not included in the above gate counts. The System Gate ranges
are derived from the following: Minimum System Gates assumes 100% of the PFU's are used for logic only (No PFU RAM) with 40% EBR
usage and 2 PLL's. Maximum System Gates assumes 80% of the PFU's are for logic, 20% are used for PFU RAM, with 80% EBR usage and
6 PLL's."
2. There are two 4K X 36 (144K bits each) RAM blocks in the embedded core which are also accessible by the FPGA logic.
Device
PFU Rows
PFU
Columns
Total PFUs
FPGA Max
User I/O
LUTs
EBR
Blocks
EBR Bits
(K)
FPGA
System
Gates (K)
1, 2
ORSO82G5
36
1296
372
10,368
12
111
333 - 643
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