参数资料
型号: M-ORSO82G51BM680-DB
厂商: LATTICE SEMICONDUCTOR CORP
元件分类: FPGA
英文描述: FPGA, 1296 CLBS, 333000 GATES, PBGA680
封装: PLASTIC, FBGA-680
文件页数: 60/123页
文件大小: 2207K
代理商: M-ORSO82G51BM680-DB
Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
41
SONET Mode Quad Alignment
Figure 26 describes the clocks and recommended clocking for quad alignment in the SONET mode. For quad
alignment, the low speed portion for each quad should be sourced by a single clock. As the gure shows, for quad
A, RSYSCLKA1 and RSYSCLKA2 should be sourced by RCK78A. For quad B, RSYSCLKB1 and RSYSCLKB2
should be sourced by RCLK78B. RCLK78A can be sourced by any channel in quad A and RCLK78B can be
sourced by any channel in quad B.
Figure 26. Receive Clocking Diagram for a Quad Channel (Quad Alignment)
RBC0
RBC1
311.04 MHz
SERDES
2.488 Gbits/s
REFCLK[P,N]
(155.52 MHz)
DEMUX
RWCKxx (77.76 MHz)
Framer,
descrambler
FPGA
Total clocks from core to FPGA
RWCKxx - 4 (one for each channel)
32b
Cell
extractor
RxFIFO
IPC8/
160b
32b
other links in quad
RCK78x
SYSCLK156[A1,A2,B1,B2,8]
Alignment
FIFO
SPE
generator
RSYSCLKx[1,2] (77.76)
where xx = [AA,AB..BD]
RCK78x - 1 for each quad where x = [A,B]
Total clocks from FPGA to core
RSYSCLKx[1,2] - 77.76MHz clock (2 for each quad) (x is A or B)
IPC2
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