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| 型号： | M-ORSO82G51BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 117/123页 |
| 文件大小： | 2207K |
| 代理商： | M-ORSO82G51BM680-DB |
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Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
93
This section describes device I/O signals to/from the embedded core.
PPC_A[14:31]
I
During MPI mode the PPC_A[14:31] are used as the address bus driven by the PowerPC bus mas-
ter utilizing the least-signicant bits of the PowerPC 32-bit address.
MPI_BURST
I
MPI_BURST is driven low to indicate a burst transfer is in progress in MPI mode. Driven high indi-
cates that the current transfer is not a burst.
MPI_BDIP
I
MPI_BDIP is driven by the PowerPC processor in MPI mode. Assertion of this pin indicates that the
second beat in front of the current one is requested by the master. Negated before the burst trans-
fer ends to abort the burst data phase.
MPI_TSZ[0:1]
I
MPI_TSZ[0:1] signals are driven by the bus master in MPI mode to indicate the data transfer size
for the transaction. Set 01 for byte, 10 for half-word, and 00 for word.
A[21:0]
O
During master parallel mode A[21:0] address the conguration EPROMs up to 4M bytes.
I/O
If not used for MPI these pins are user-programmable I/O pins after conguration.*
MPI_ACK
O
In
MPI mode this is driven low indicating the MPI received the data on the write cycle or returned
data on a read cycle.
I/O
If not used for MPI these pins are user-programmable I/O pins after conguration.*
MPI_CLK
I
This is the PowerPC synchronous, positive-edge bus clock used for the MPI interface. It
can be a source of the clock for the Embedded System Bus. If MPI is used this will be the
AMBA bus clock.
I/O
If not used for MPI these pins are user-programmable I/O pins after conguration.*
MPI_TEA
O
A low on the MPI transfer error acknowledge indicates that the MPI detects a bus error on the inter-
nal system bus for the current transaction.
I/O
If not used for MPI these pins are user-programmable I/O pins after conguration.*
MPI_RTRY
O
This pin requests the MPC860 to relinquish the bus and retry the cycle.
I/O
If not used for MPI these pins are user-programmable I/O pins after conguration.*
D[0:31]
I/O
Selectable data bu
s width from 8, 16, 32-bit in MPI mode. Driven by the bus master in a write trans-
action and driven by MPI in a read transaction.
I
D[7:0] receive conguration data during master parallel, peripheral, and slave parallel conguration
modes when WR is low and each pin has a pull-up enabled. During serial conguration modes, D0
is the DIN input.
O
D[7:3] output internal status for asynchronous peripheral mode when RD is low.
I/O
After conguration, if MPI is not used, the pins are user-programmable I/O pins.*
DP[0:3]
I/O
Selectable parity bus width in MPI mode from 1, 2, 4-bit, DP[0] for D[0:7], DP[1] for D[8:15], DP[2]
for D[16:23], and DP[3] for D[24:31].
After conguration, if MPI is not used, the pins are user-programmable I/O pin.*
DIN
I
During slave serial or master serial conguration modes, DIN accepts serial conguration data syn-
chronous with CCLK. During parallel conguration modes, DIN is the D0 input. During congura-
tion, a pull-up is enabled.
I/O
After conguration, this pin is a user-programmable I/O pin.*
DOUT
O
During conguration, DOUT is the serial data output that can drive the DIN of daisy-chained slave
devices. Data out on DOUT changes on the rising edge of CCLK.
I/O
After conguration, DOUT is a user-programmable I/O pin.*
TESTCFG
I
During conguration this pin should be held high, to allow conguration to occur. A pull up is
enabled during conguration.
I/O
After conguration, TESTCFG is a user programmable I/O pin.*
Symbol
I/O
Description
* The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE release
is controlled by one set of bit stream options, and the timing of the simultaneous release of all other conguration pins (and the activation of all
user I/Os) is controlled by a second set of options.
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