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| 型号： | M-ORSO82G51BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 55/123页 |
| 文件大小： | 2207K |
| 代理商： | M-ORSO82G51BM680-DB |
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Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
37
channel will have an associated clock (RWCKxx at 77.76 MHz). Each channel will also provide a FP and SPE
indicator along with the data. Descrambling can be inhibited through the DSCR_INH_xx control bit.
Data can be sent directly from the 8:32 DEMUX block to the FPGA bypassing the alignment FIFO and SONET
framer and descrambler. Data from each channel will have an associated clock. No SPE or FP indicator is pro-
vided with the data.
Receive FIFO in SONET mode
The receive FIFO used in SONET mode will allow for an inter-link skew of about 300 ns (24 x 32 = 768 bits, 400 ps
per bit gives 307 ns). The FIFO is written at 77.76 MHz and read at 77.76 MHz. Once frame synchronization has
occurred, the write control logic will cause data to be written to the memory. The write control block is required to
insure that the word containing the rst A1 byte is written to the same location (address 0) in the FIFO. The syn-
chronization algorithm issues a sync pulse and sync error signals to the read control block based on the alignment
option chosen (align all 8, align by 4 or align by pairs). This sync pulse will coordinate the reading of the FIFOs.
The read control logic synchronizes the reading of the FIFO for the streams that are to be aligned. The block begins
reading with the FIFO sync sub block signals that all of the applicable A1s with the appropriate margin have been
written to the FIFO. All of the read blocks to be synchronized begin reading at the same time and same location in
the memory (address 0). The block also takes the difference between the write and read address to indicate the rel-
ative skews between the links. If this difference exceeds a certain limit (programmable), then an alarm (alignment
overow) is provided to the register interface.
Multi-channel Alignment in SONET Mode
The alignment FIFO allows the transfer of all data to a common clock. The FIFO sync block allows the system to be
congured to allow the frame alignment of multiple slightly varying data streams. This optional alignment ensures
that matching SERDES streams will arrive at the FPGA end in perfect data sync. It is important to note that for all
aligned channels in a group, the SERDES transmitters on the other side of the high-speed link must all be transmit-
ting data at exactly the same frequency (0 ppm difference), i.e., using a common clock source.
The ORSO82G5 has a total of 8 channels (4 per quad SERDES). The incoming data of these channels can be syn-
chronized in several ways, or they can be independent of one other. Two channels within a SERDES can be aligned
together; channel A and B and/or channel C and D can form a pair as shown in Figure 22. Alternately, all four chan-
nels in a SERDES quad can be aligned together to form a communication channel with a bandwidth of 10 Gbits/s
as shown in Figure 23.
Finally, the alignment can be extended across SERDES to align all 8 channels in ORSO82G5 as shown in
Figure 23. Individual channels within an alignment group can be disabled (i.e., powered-down) without disrupting
other channels. Note that the SERDES channel that is powered down can not be the source of the RSYSCLKxx
that is clocking the read side of the alignment FIFO. When a disabled channel becomes active as part of an align-
ment group, the group may need to be re-aligned. Then the whole group needs to be resynched. This would only
need to occur if the transmitting frame pulse for the new link is different from the rest of the group.
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