参数资料
型号: M-ORSO82G51BM680-DB
厂商: LATTICE SEMICONDUCTOR CORP
元件分类: FPGA
英文描述: FPGA, 1296 CLBS, 333000 GATES, PBGA680
封装: PLASTIC, FBGA-680
文件页数: 80/123页
文件大小: 2207K
代理商: M-ORSO82G51BM680-DB
Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
6
Programmable Logic System Features
Improved PowerPC
860 and PowerPC II high-speed synchronous MicroProcessor Interface can be used for
conguration, readback, device control, and device status, as well as for a general-purpose interface to the
FPGA logic, RAMs, and embedded standard cell blocks. Glueless interface to synchronous PowerPC processors
with user-congurable address space provided.
New embedded AMBA specication 2.0 AHB system bus (ARM
processor) facilitates communication among
the MicroProcessor Interface, conguration logic, Embedded Block RAM, FPGA logic, and embedded standard
cell blocks.
Variable size bused readback of conguration data capability with the built-in MicroProcessor Interface and sys-
tem bus.
Internal, 3-state, and bidirectional buses with simple control provided by the SLIC.
New clock routing structures for global and local clocking signicantly increases speed and reduces skew.
New local clock routing structures allow creation of localized clock trees.
Two new edge clock routing structures allow up to six high-speed clocks on each edge of the device for improved
setup/hold and clock to out performance.
New Double-Data Rate (DDR) and zero-bus turn-around (ZBT) memory interfaces support the latest high-speed
memory interfaces.
New 2x/4x uplink and downlink I/O capabilities interface high-speed external I/Os to reduced speed internal
logic.
ispLEVER development system software. Supported by industry-standard CAE tools for design entry, synthesis,
simulation, and timing analysis.
Meets Universal Test and Operations PHY Interface for ATM (UTOPIA) levels 1, 2, and 3; as well as POS-PHY3.
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