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| 型号： | M-ORSO82G51BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 29/123页 |
| 文件大小： | 2207K |
| 代理商： | M-ORSO82G51BM680-DB |
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Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
13
ORSO82G5 Main Operating Modes - Overview
The ORSO82G5 supports eight 1.0 to 2.7 Gbits/s serial data channels which can operate independently or can be
combined together (aligned) to achieve higher bit rates. The mode of operation of the core is dened by a set of
control registers, which can be written through the system bus interface. The status of the core is stored in a set of
status registers, which can be read through the system bus interface.
The 8 serial data channels supports OC-48 rates on each channel. OC-192 is also supported but is transmitted
and received in quad OC-48 links. The 2.488 Gbits/s scrambled data stream conforms to the GR-255 specied
polynomial sequence of 1+x
6+x7.
There are three main operating modes in the ORSO82G5 as described below:
SERDES only (bypass) mode
SONET mode
Cell mode
–Two-link sub-mode
– Eight-link sub-mode
There are sub-modes that can be derived by enabling or disabling certain functions through programmable register
bits. Also, in Cell mode, either the two-link alignment mode, for up to four alignment groups, or the eight-link align-
ment mode, where all eight links are combined into a single group, may be selected.
Data are processed in the transmit direction (FPGA to Backplane) as follows:
In the SERDES only mode, there is the option to bypass all of the SONET and cell functions and pass raw 32-bit
data from the FPGA into the 32:8 MUX block. In this mode, the user is responsible for providing an adequate
ones transition density in the transmitted stream for clock and data recovery at the receive end of the link.
In the SONET mode, a SONET frame is constructed around the input data and overhead bytes are inserted
where appropriate. The 32-bits of data per channel are scrambled before being converted to 8-bits by the 32:8
MUX block and serialized by the SERDES.
In the cell mode, 160 bits of data from the FPGA is sent to the Output Port Controller-8 block (also referred to as
OPC8 since it services eight links) or 40 bits of data to Output Port Controller-2 block (referred to as
OPC2_[A1,A2,B1,B2]) which perform cell striping across the different SERDES links. The cells are then trans-
ferred to the SONET clock domain of 77.76 MHz through a Transmit FIFO. A SONET frame is constructed
around the cell payload and overhead bytes inserted where appropriate before being sent to the MUX block. The
data are then converted to 8 bits by the 32:8 MUX block before being serialized by the SERDES.
Data are processed in the receive direction (Backplane to FPGA) as follows:
In the SERDES only mode, there is the option to bypass all of the SONET and cell functions and pass raw 32-bit
data from the 8:32 DEMUX block into the FPGA interface.
In the SONET mode, the descrambled data are sent to an alignment FIFO that performs lane-to-lane deskew
and aligns data within an alignment group to a single clock domain and frame pulse. The SPE indicator is pro-
vided to the FPGA along with 32 bits of aligned data.There is an option to bypass the alignment FIFOs and pass
data directly from the descrambler to the FPGA. This mode is programmable and can be controlled per channel.
In the cell mode, the SONET framed data are descrambled and passed into a cell extractor which extracts cells
from the payload portion of the SONET frame. The cells are passed through a FIFO which performs lane-to-lane
deskew and a clock domain transfer from 77.76 MHz to 156 MHz. The cells are passed into the input port con-
troller block (referred to as IPC8 or IPC2_[A1, A2, B1, B2] depending on whether 8 or two links are serviced)
which performs cell destriping before sending them to the FPGA interface. This cell processing feature makes
ORSO82G5 ideal for interfacing devices with proprietary data formats across a backplane.
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