- 您现在的位置：买卖IC网 > PDF目录180051 > M-ORSO82G51BM680-DB (LATTICE SEMICONDUCTOR CORP) FPGA, 1296 CLBS, 333000 GATES, PBGA680 PDF资料下载
参数资料
| 型号： | M-ORSO82G51BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 68/123页 |
| 文件大小： | 2207K |
| 代理商： | M-ORSO82G51BM680-DB |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页当前第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页
Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
49
number 37. The cell will be marked with an error. The receiver then expects to receive a cell with sequence number
28.
Cell Mode Transmit Path
In the transmit path in cell mode, the transmit logic creates a SONET-like transport frame for the data, adds the
required Transport OverHead bytes (cell mode automatically uses AUTO_TOH mode) and retimes the cell data
from the FPGA interface rate of 156 MHz to the framer rate of 77.76 MHz. The data are then sent to the SONET
logic blocks and SERDES. The Payload sub-block of the SONET logic operates somewhat differently than in
SONET mode, however.
Output Port Controller
In cell mode the Output Port Controller (OPC) is the block responsible for directing trafc for the egress cell trafc
ow. These are the blocks that provides the interface between FPGA and the Transmit FIFO. There is one eight-
link controller (OPC8) and four two-link controllers (OPC2s). The user provides the 160-bit (OPC8) or 40-bit
(OPC2) cell data, and a cell_vaild strobe to the OPC. No Link Header byte is sent with the cell data. The OPC pro-
vides the following functions:
Accepts cell payload from the FPGA logic and assembles legal output cells from these.
Schedules, manages and performs writes of cell data into TX FIFOs in the transmit framer blocks of all the eight-
links or up to 4 pairs of two-links.
Provides backpressure information to the FPGA to stop writes to the TXFIFO if the FIFO is not ready to accept
data.
The 5 OPC blocks operate as follows:
OPC8 to stripe cells across eight-links
OPC2_A1 to service links AA,AB
OPC2_A2 to service links AC,AD
OPC2_B1 to service links BA,BB
OPC2_B2 to service links BC,BD
When operating with some links in the two-link cell mode, links not in an alignment group can optionally be oper-
ated in a SONET mode.
The OPC2 blocks run at 39 MHz. The input from FPGA is a 40-bit bus at 156 MHz (4 times the required frequency).
A 1:4 deMUX block provides a 160-bit bus at 39 MHz
相关PDF资料 |
PDF描述 |
|---|---|
| M-ORSO82G52BM680-DB | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| M-ORT82G51BM680-DB | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| M-ORT82G52BM680-DB | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| M.PI-1R1D12 | 1 ELEMENT, 1.1 uH, GENERAL PURPOSE INDUCTOR, SMD |
| M01-014-1452PA | 14 CONTACT(S), MALE, RIGHT ANGLE TELECOM AND DATACOM CONNECTOR, SOLDER |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MORTAR-44LB | 制造商:3M Electronic Products Division 功能描述:3M(TM) FIRE BARRIER MORTAR, 44 98040056073 制造商:3M Electronic Products Division 功能描述:Fire Barrier 44 lb Bag |
| MO-RX3930 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FSK RECEIVER MODULE |
| MO-RX3930-FS | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FSK RECEIVER MODULE |
| MO-RX3930-FS315M | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FSK RECEIVER MODULE |
| MO-RX3930-FS434M | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FSK RECEIVER MODULE |
发布紧急采购，3分钟左右您将得到回复。