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| 型号： | M-ORSO82G51BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 108/123页 |
| 文件大小： | 2207K |
| 代理商： | M-ORSO82G51BM680-DB |
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Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
85
Table 22. Common Status Register Descriptions
(0x) Abso-
lute
Address
Bit
Name
Reset
Value
(0x)
Description
Mode
Common Status Registers (Read Only)
30A08
[0]
ALARM_STATUS_BD
00
Alarm Status Indicator, This bit is an OR of all
alarm status bits for the channel BD. A 1 on this
bit will also set the alarm pin on the system bus
interrupt cause register (on the FPGA side).
Both
[1]
ALARM_STATUS_BC
Alarm Status Indicator, This bit is an OR of all
alarm status bits for the channel BC. A 1 on this
bit will also set the alarm pin on the system bus
interrupt cause register (on the FPGA side).
Both
[2]
ALARM_STATUS_BB
Alarm Status Indicator, This bit is an OR of all
alarm status bits for the channel BB. A 1 on this
bit will also set the alarm pin on the system bus
interrupt cause register (on the FPGA side).
Both
[3]
ALARM_STATUS_BA
Alarm Status Indicator, This bit is an OR of all
alarm status bits for the channel BA. A 1 on this
bit will also set the alarm pin on the system bus
interrupt cause register (on the FPGA side).
Both
[4]
ALARM_STATUS_AD
Alarm Status Indicator, This bit is an OR of all
alarm status bits for the channel AD. A 1 on this
bit will also set the alarm pin on the system bus
interrupt cause register (on the FPGA side).
Both
[5]
ALARM_STATUS_AC
Alarm Status Indicator, This bit is an OR of all
alarm status bits for the channel AC. A 1 on this
bit will also set the alarm pin on the system bus
interrupt cause register (on the FPGA side).
Both
[6]
ALARM_STATUS_AB
OR of all alarm status bits for channel AB. A 1
on this bit will set the alarm pin on the system
bus interrupt cause register (on the FPGA side)
Both
[7]
ALARM_STATUS_AA
Alarm Status Indicator, This bit is an OR of all
alarm status bits for the channel AA. A 1 on this
bit will also set the alarm pin on the system bus
interrupt cause register (on the FPGA side).
Both
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