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参数资料
| 型号： | M-ORSO82G51BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 92/123页 |
| 文件大小： | 2207K |
| 代理商： | M-ORSO82G51BM680-DB |
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Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
70
Table 15. SERDES Per-Channel Transmit Conguration Register Descriptions
Table 16. SERDES Per-Channel Receive Conguration Register Descriptions
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
Mode
SERDES Transmit Per-Channel Conguration Registers (Read/Write) xx = [AA, ...,BD]
30002 - AA
30012 - AB
30022 - AC
30032 - AD
30102 - BA
30112 - BB
30122 - BC
30132 - BD
[0]
TXHR_xx
00
Transmit Half Rate Selection Bit, Channel xx.
When TXHR_xx = 1, HDOUT_xx's baud rate =
(REFCLK[A:B]*8) and TCK78[A:B] =(REF-
CLK[A:B]/4); when TXHR_xx=0, HDOUT_xx's
baud rate = (REFCLK[A:B]*16) and
TCK78[A:B]=(REFCLK[A:B]/2).
TXHR_xx = 0 on device reset.
Both
[1]
PWRDNT_xx
Transmit Powerdown Control Bit, Channel xx.
When PWRDNT_xx = 1, sections of the trans-
mit hardware are powered down.
PWRDNT_xx = 0 on device reset.
Both
[2]
PE0_xx
Transmit Preemphasis Selection Bit 0, Channel
xx. PE0_xx and PE1_xx select one of three
preemphasis settings for the transmit section.
PEO_xx=PE1_xx = 0, Preemphasis is 0%
PEO_xx=1, PE1_xx = 0 or PEO_xx=0,
PE1_xx = 1, Preemphasis is 12.5%
PEO_xx=PE1_xx = 1, Preemphasis is 25%.
PEO_xx=PE1_xx = 0 on device reset.
Both
[3]
PE1_xx
Both
[4]
HAMP_xx
Transmit Half Amplitude Selection Bit, Channel
xx. When HAMP_xx = 1, the transmit output
buffer voltage swing is limited to half its normal
amplitude. Otherwise, the transmit output buffer
maintains its full voltage swing.
HAMP_xx = 0 on device reset.
Both
[5:7]
RSVD
Reserved, Always set to "000"
(0x) Abso-
lute
Address
Bit
Name
Reset
Value
(0x)
Description
Mode
SERDES Receive Per-Channel Conguration Registers (Read/Write) xx = [AA, ...,BD]
30003 - AA
30013 - AB
30023 - AC
30033 - AD
30103 - BA
30113 - BB
30123 - BC
30133 - BD
[0]
RXHR_xx
20
Receive Half Rate Selection Bit, Channel xx.
When RXHR_xx =1, HDIN_xx's baud rate =
(REFCLK[A:B]*8) and RCK78[A:B]=(REF-
CLK[A:B]/4); When RXHR_xx=0, HDIN_xx's baud
rate = (REFCLK[A:B]*16) and RCK78[A:B]=(REF-
CLK/2).
RXHR_xx = 0 on device reset.
Both
[1]
PWRDNR_xx
Receiver Power Down Control Bit, Channel xx.
When PWRDNR_xx = 1, sections of the receive
hardware are powered down. PWRDNR_xx = 0
on device reset.
Both
[2:7]
RSVD
Reserved (Bit 2 = 1 on device reset)
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