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参数资料
| 型号： | M-ORSO82G51BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 86/123页 |
| 文件大小： | 2207K |
| 代理商： | M-ORSO82G51BM680-DB |
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Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
65
Embedded Core Block RAM
There are two independent memory slices (labeled A and B) in the embedded core. Each memory slice has a
capacity of 4K words by 36 bits. These are in addition to the block RAMs found in the FPGA portion of the
ORSO82G5. Although the memory slices are in the embedded core part of the chip, they do not interact with the
rest of the embedded core circuits, but are standalone memories designed specically to increase RAM capacity in
the ORSO82G5 chip. They can be used by the soft IP cores implemented in the FPGA portion of the FPSC.
A block diagram of a memory slice is shown in Figure 45. Each memory slice is organized into two sections
(labeled SRAM A and SRAM B) and has one read port, one write port and four byte-write-enable (active-low) sig-
nals. Each byte has eight data bits and a control/parity bit. The control/parity bit responds to the same byte enable
(BYTEWN_x[x]) as it’s corresponding data. No special logic such as parity checking is performed on this bit by the
core. The read data from the memory is registered so that it works as a pipelined synchronous memory block. The
minimum timing specications are shown in Figure 46 and Figure 47. Signal names and functions are summarized
later in Table 12 and follow the general Series 4 naming conventions.
Figure 45. Block Diagram, Embedded Core Memory Slice
4K x 36
D_x[35:0]
Memory Slice
(1 of 2)
2K x 36 Memory
(SRAM A)
(SRAM B)
Write Ports
CKW_x
CSWA_x
CSWB_x
AW_x[10:0]
BYTEWN_x[3]
BW[35,31:24]
BYTEWN_x[2]
BW[34,23:16]
BYTEWN_x[1]
BW[33,15:8]
BYTEWN_x[0]
BW[32,7:0]
Q_x[35:0]
CKR_x
CSR_x
AR_x[10:0]
Read Ports
Side A /
Write Selects
Side B
FPGA
Logic
RAM Block
Read Selects
36
11
36
11
Note: x=[A,B] Slice Identifier
Parity
Data
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