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| 型号： | M-ORSO82G51BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 104/123页 |
| 文件大小： | 2207K |
| 代理商： | M-ORSO82G51BM680-DB |
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Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
81
Table 21. Common Control Register Descriptions
(0x) Abso-
lute
Address
Bit
Name
Reset
Value
(0x)
Description
Mode
Common Control Registers (Read/Write)
30A00
[0:1]
RCKSELB
00
“00” - Channel BA source for clock RCK78B
“01” - Channel BB source for clock RCK78B
“10” - Channel BC source for clock RCK78B
“11” - Channel BD source for clock RCK78B
Both
[2:3]
TCKSELB
“00” - Channel BA source for clock TCK78B
“01” - Channel BB source for clock TCK78B
“10” - Channel BC source for clock TCK78B
“11” - Channel BD source for clock TCK78B
Both
[4:5]
RCKSELA
“00” - Channel AA source for clock RCK78A
“01” - Channel AB source for clock RCK78A
“10” - Channel AC source for clock RCK78A
“11” - Channel AD source for clock RCK78A
Both
[6:7]
TCKSELA
“00” - Channel AA source for clock TCK78A
“01” - Channel AB source for clock TCK78A
“10” - Channel AC source for clock TCK78A
“11” - Channel AD source for clock TCK78A
Both
30A01
[0:2]
CELL_SIZE
00
Cell Size, Three bits to set cell size.
“000” - Cell size is 76 bytes,
“001” - Cell size is 80 bytes,
“010” - Cell size is 84 bytes,
“011” - Cell size is 92 bytes
These are the only supported cell sizes.
Cell
[3:7]
RX_FIFO_MIN
Set Minimum threshold value for alignment
FIFO in SONET mode. When the read address
for the FIFO is below this value at the time
when write address is zero, it indicates that the
FIFO is near overow. This event will go high
only once during a frame when a framing byte
has been detected by the aligner. The default
threshold value is “00000”.
SONET
30A02
0
TX_DISABLE_ON_RDI
01
Transmitter Disable on RDI (Detection), If
TX_DISABLE_ON_RDI = 1 - No cell data is
transmitted on a link in which a RDI has been
detected by the corresponding link’s receiver. If
this bit is set to 0, cell data will be transmitted
on a link irrespective of detection of a RDI.
Cell
[1:3]
DEVICE_MODE
These bits should always be set to “001”
Cell
4
SCHAR_ENA
SCHAR_ENA = 1 enables SERDES character-
ization of SERDES B. Refer to section
Both
5
SCHAR_TXSEL
SCHAR_TXSEL =1 is a Select Tx option which
will cause chip ports to directly control the
SERDES low-speed transmit ports of one of
the channels selected by SCHAR_CHAN
Both
6:7
SCHAR_CHAN
“00” - Select channel BA to test
“01” - Select channel BB to test
“10” - Select channel BC to test
“11” - Select channel BD to test
Both
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