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| 型号： | M-ORSO82G51BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 91/123页 |
| 文件大小： | 2207K |
| 代理商： | M-ORSO82G51BM680-DB |
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Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
7
Description
What Is an FPSC?
FPSCs, or Field-Programmable System Chips, are devices that combine eld-programmable logic with ASIC or
mask-programmed logic on a single device. FPSCs provide the time to market and the exibility of FPGAs, the
design effort savings of using soft Intellectual Property (IP) cores, and the speed, design density, and economy of
ASICs.
FPSC Overview
Lattice’s Series 4 FPSCs are created from Series 4 ORCA FPGAs. To create a Series 4 FPSC, several columns of
Programmable Logic Cells (see FPGA Logic Overview section for FPGA logic details) are added to an embedded
logic core. Other than replacing some FPGA gates with ASIC gates, at greater than 10:1 efciency, none of the
FPGA functionality is changed—all of the Series 4 FPGA capability is retained: Embedded Block RAMs, MPI,
PCMs, boundary scan, etc. The columns of programmable logic are replaced at the right of the device, allowing
pins from the replaced columns to be used as I/O pins for the embedded core. The remainder of the device pins
retain their FPGA functionality.
FPSC Gate Counting
The total gate count for an FPSC is the sum of its embedded core (standard-cell/ASIC gates) and its FPGA gates.
Because FPGA gates are generally expressed as a usable range with a nominal value, the total FPSC gate count
is sometimes expressed in the same manner. Standard-cell ASIC gates are, however, 10 to 25 times more silicon-
area efcient than FPGA gates. Therefore, an FPSC with an embedded function is gate equivalent to an FPGA with
a much larger gate count.
FPGA/Embedded Core Interface
The interface between the FPGA logic and the embedded core has been enhanced to allow for a greater number of
interface signals than on previous FPSC architectures. Compared to bringing embedded core signals off-chip, this
on-chip interface is much faster and requires less power. All of the delays for the interface are precharacterized and
accounted for in the ispLEVER Development System.
ORCA Series 4 based FPSCs expand this interface by providing a link between the embedded block and the multi-
master 32-bit system bus in the FPGA logic. This system bus allows the core easy access to many of the FPGA
logic functions including the Embedded Block RAMs and the MicroProcessor Interface.
Clock spines also can pass across the FPGA/embedded core boundary. This allows for fast, low-skew clocking
between the FPGA and the embedded core. Many of the special signals from the FPGA, such as DONE and global
set/reset, are also available to the embedded core, making it possible to fully integrate the embedded core with the
FPGA as a system.
For even greater system exibility, FPGA conguration RAMs are available for use by the embedded core. This
allows for user-programmable options in the embedded core, in turn allowing for greater exibility. Multiple embed-
ded core congurations may be designed into a single device with user-programmable control over which congu-
rations are implemented, as well as the capability to change core functionality simply by reconguring the device.
ispLEVER Development System
The ispLEVER development system is used to process a design from a netlist to a congured FPGA. This system
is used to map a design onto the ORCA architecture, and then place and route it using ispLEVER development
system timing-driven tools. The development system also includes interfaces to, and libraries for, other popular
CAE tools for design entry, synthesis, simulation, and timing analysis.
FPSC Design Kit
Development is facilitated by an FPSC design kit which, together with ispLEVER and third-party synthesis and sim-
ulation engines, provides all software and documentation required to design and verify an FPSC implementation.
Included in the kit are the FPSC conguration manager, Synopsys Smart Model
, and/or complied Verilog simula-
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