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| 型号： | M-ORSO82G51BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 58/123页 |
| 文件大小： | 2207K |
| 代理商： | M-ORSO82G51BM680-DB |
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Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
4
– 85 bytes per cell (83 bytes of data payload)
– 93 bytes per cell (91 bytes of data payload)
Automatic cell striping across either pairs of SERDES links or all eight SERDES links.
Addition of two 4K X 36 dual-port RAMs with access to the programmable logic.
Programmable Features
High-performance programmable logic:
– 0.16 m 7-level metal technology.
– Internal performance of >250 MHz.
–Over 600K usable system gates.
– Meets multiple I/O interface standards.
– 1.5 V operation (30% less power than 1.8 V operation) translates to greater performance.
Traditional I/O selections:
–LVTTL (3.3V) and LVCMOS (2.5 V, and 1.8 V) I/Os.
–Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance.
– Individually programmable drive capability:
24 mA sink/12 mA source, 12 mA sink/6 mA source, or 6 mA sink/3 mA source.
–Two slew rates supported (fast and slew-limited).
–Fast-capture input latch and input Flip-Flop (FF)/latch for reduced input setup time and zero hold time.
–Fast open-drain drive capability.
– Capability to register 3-state enable signal.
– Off-chip clock drive capability.
–Two-input function generator in output path.
New programmable high-speed I/O:
– Single-ended: GTL, GTL+, PECL, SSTL3/2
(class I and II), HSTL (Class I, III, IV), ZBT, and DDR.
– Double-ended: LVDS, bused-LVDS, and LVPECL. Programmable (on/off), internal parallel termination (100
) is also supported for these I/Os.
New capability to (de)multiplex I/O signals:
–New DDR on both input and output at rates up to 350 MHz (700 MHz effective rate).
–New 2x and 4x downlink and uplink capability per I/O (i.e., 50 MHz internal to 200 MHz I/O).
Enhanced twin-quad Programmable Function Unit (PFU):
– Eight 16-bit Look-Up Tables (LUTs) per PFU.
– Nine user registers per PFU, one following each LUT, and organized to allow two nibbles to act indepen-
dently, plus one extra for arithmetic operations.
–New register control in each PFU has two independent programmable clocks, clock enables, local set/reset,
and data selects.
–New LUT structure allows exible combinations of LUT4, LUT5, new LUT6, 4 → 1 MUX, new 8 → 1 MUX,
and ripple mode arithmetic functions in the same PFU.
– 32 x 4 RAM per PFU, congurable as single-port or dual-port. Create large, fast RAM/ROM blocks (128 x 8
in only eight PFUs) using the SLIC decoders as bank drivers.
– Soft-Wired LUTs (SWL) allow fast cascading of up to three levels of LUT logic in a single PFU through fast
internal routing which reduces routing congestion and improves speed.
– Flexible fast access to PFU inputs from routing.
–Fast-carry logic and routing to all four adjacent PFUs for nibble-wide, byte-wide, or longer arithmetic func-
tions, with the option to register the PFU carry-out.
Abundant high-speed buffered and nonbuffered routing resources provide 2x average speed improvements over
previous architectures.
Hierarchical routing optimized for both local and global routing with dedicated routing resources. This results in
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