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参数资料
| 型号： | M-ORSO82G51BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 53/123页 |
| 文件大小： | 2207K |
| 代理商： | M-ORSO82G51BM680-DB |
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Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
35
SONET Mode Receive Path
The receiver block receives a byte from the SERDES blocks for each of the eight channels. The byte arrives at the
receiver block at 311.04 MHz. This data are not frame-aligned or word aligned. The data are rst passed through a
divide-by-4 DEMUX which produces a 32-bit word at 77.76 MHz. Data from the DEMUX is then passed through a
framer which aligns and frames the data. Data are processed based on cell mode or SONET mode.
In the SONET mode, the descrambled data are sent to an alignment FIFO that performs lane-to-lane deskew and
aligns data within an alignment group to the RSYCLK[A1, A2, B1, B2] clock domain. Both the write and read clocks
to the alignment FIFO should be at exactly the same frequency (0 ppm difference), i.e., from a common clock
source. Later in this datasheet, Figures 25, 26, and 27 show the recommended clocking scheme to adhere to this
requirement. In addition, supervisory features such as BIP error check, OOF check, RDI monitoring and AIS-L
insertion during OOF are also implemented. All the supervisory features are controlled through programmable reg-
ister bits.
Framer
The frame and byte phase of the bits within the 32-bit word from the DEMUX is random. For each of the STS-48
channels, the framer outputs 4 bytes (32-bits) that are frame-aligned and a frame pulse that is one clock-wide. The
transition from A1 bytes to A2 bytes should happen on a 32-bit boundary. If any two consecutive bytes of the 4-
byte-aligned word match the A1-A2 pattern (0xF628 in standard SONET framing), the byte-aligned word will be
byte rotated to achieve frame alignment.
Framer State Machine (FSM)
The framer FSM is responsible for detecting the in-frame and Out-Of-Frame status of the incoming data and sends
out alarms (interrupts) on Out-Of-Frame (OOF). The framer is a pseudo-SONET framer in the sense that it does
not support LOF or SEF detect-alarm signal as specied in the GR-253 standard.
The framer has a fast frame mode where a single good framing pattern can cause the framer state machine to go
the “in_frm” state and a single bad frame can cause the state machine to declare “OOF” (See Fig. 21). The fast
frame mode can be set by the software register bit, FFRM_EN_xx.
The FSM is a four byte framer and searches for the framing pattern based on the 32-bit words. Accordingly, the
framing pattern is four A1 bytes (F6,F6,F6,F6) followed by four A2 bytes (28,28,28,28).
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