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| 型号： | M-ORSO82G51BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 77/123页 |
| 文件大小： | 2207K |
| 代理商： | M-ORSO82G51BM680-DB |
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Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
57
Figure 42. ORSO82G5 Receive FPGA/Embedded Core Interface IPC2 Mode
When operating in CELL MODE, the IPC2 Block passes user cells as well as control and status signals to the user.
Depending upon the congured CELL SIZE, cell transfers will take a variable number of SYSCLK156 cycles to be
received across the interface. Data are always transferred across a 40-bit bus (5 octets per clock cycle). Figure 42
shows 16 clock cycles for a cell transfer. This corresponds to a User Cell size of 79 octets.
Figure 43 shows cell octal alignment mode timing. When operating in CELL MODE, the IPC8 Block aligns all 8
channels of receive data on a FRAME basis. The IPC8 also passes user cells as well as control and status signals
to the user. Depending upon the congured CELL SIZE, cell transfers will take a variable number of SYSCLK156
cycles to be received across the interface. Data are always transferred across an 160-bit bus (20 octets per clock
cycle). Figure 43 shows 4clock cycles for a cell transfer. This corresponds to a User Cell size of 79 octets.
Figure 43. ORSO82G5 Receive FPGA/Embedded Core Interface IPC8 Mode
SYSCLK156x[1,2]
IPC2_A[1,2]CELLSTART
D
DDD
D
DD
D
DD
D
DDDD
4 clk cycles
“n” clk cycles
4 clk cycles
CELL BIP ERROR
If a Cell BIP Error occurs,
the CELL_BIP_ERR signal reects the occurrence, as shown in the
Figure.
For 2-Link CELL MODE,
the CELL_BIP_ERR signal is asserted during the last 4 clock cycles
of the receive cell.
4 clk cycles
D
IPC2_A[1,2]_BIP_ERR
IPC2_A[1,2]_CELLDROP
IPC2_x[1,2][39:0]
BIP Error is associated
with CURRENT cell
Cell Drop is associated with
the NEXT cell (NOT present)
CELL BIP ERROR
If a cell error occurs within the ASB and;
1. CELL_BIP_INH=0 ...Do not drop BIP errored cells
(s/w selectable)
2. A BIP error occurs
The drop indicator will PRECEED the user cell that con-
tains the BIP error. All data will be passed w/o modica-
tion.
SYSCLK156x[1,2]
IPC8_CELLSTART
D
DDD
D
DD
D
DD
D
DDDD
“n” clk cycles
4 clk cycles
CELL BIP ERROR
If a Cell BIP Error occurs,
the CELL_BIP_ERR signal reects the occurrence, as shown in the
Figure.
For 2-Link CELL MODE,
the CELL_BIP_ERR signal is asserted during the last 4 clock cycles
of the receive cell.
D
IPC8_CELL_BIP_ERR
IPC8_CELLDROP
IPC8_[159:0]
BIP Error is associated
with CURRENT cell
Cell Drop is associated with
the NEXT cell (NOT present)
CELL BIP ERROR
If a cell error occurs within the ASB and;
1. CELL_BIP_INH=0 (Do not drop BIP errored cells)
2. A BIP error occurs
The drop indicator will PRECEED the user cell that con-
tains the BIP error. All data will be passed w/o modica-
tion.
1 cycle
IDLE
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