- 您现在的位置：买卖IC网 > PDF目录180051 > M-ORSO82G51BM680-DB (LATTICE SEMICONDUCTOR CORP) FPGA, 1296 CLBS, 333000 GATES, PBGA680 PDF资料下载
参数资料
| 型号： | M-ORSO82G51BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 74/123页 |
| 文件大小： | 2207K |
| 代理商： | M-ORSO82G51BM680-DB |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页当前第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页
Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
54
Cell Extractor
This block is used only in cell mode and does the following:
Extracts User cells from the SPE
Performs BIP calculation/checks to verify cell integrity
Link Header Sequence Interrogation
Processing options include:
Cell handling for invalid sequence (drop or pass to FPGA)
S/W congurable ‘link removal’ due to excessive sequence errors
Data from the cell extractor block(s) is sent to the receive FIFO which aligns the data to the system clock domain
and provides for deskew between the links.
Cell Extraction and BIP Calculation/Checking
The data from the descrambler are passed into the data extractor which strips the cell data from the payload of a
SONET frame. The block extracts the BIP value from the data stream and also perform an internal cell BIP calcula-
tion. The block also determines when the next Link Header is coming in the frame and what the cell sequence num-
ber contained within it should be. If the value of the cell sequence counter is not equal to the expected value, then
an error ag will be sent to the software register interface.
Link Header Detector
The Link Header detector determines when the next Link Header is coming in the frame and what the sequence
number contained within it should be. If the value of the cell sequence counter is not equal to the expected value,
then an alarm signal will be set to the register map, and increment the sequence counter to the next sequence
number. The sequence count value is NOT updated with the incorrect value, but is incremented each time a Link
Header is received.
If excessive sequence errors are detected (three or more), and the AUTO_REMOVE register bit is set then the cor-
responding link will be treated as not valid. If while the link is in the invalid state, 3 consecutive valid sequence num-
bers are detected, and (the AUTO_REJOIN register bit is set) then the link is again valid. If the AUTO_REMOVE
register bit is not set then the link is still valid when excessive sequence errors are detected. While trying to regain
sequence number synchronization the sequence number used for comparison will be reloaded from the Link
Header until synchronization is achieved.
Receive FIFO
The main clock domain transfer for the data path is handled by the receive FIFO. A 16 x 161 FIFO is used in cell
mode. The FIFO is implemented as a dual-port memory which will support simultaneous reads and writes. The
receive FIFO block is written to at 77.76 MHz and read at 156 MHz.
The receive FIFO can allow for inter-link skew of about 800 ns (16 x 160 = 2560 bits, 400 ps per bit gives 1024 ns).
The 160 LSBs in the memory are received data and the 161st bit indicates the start of a new cell. The FIFO write
control logic indicates to the IPC, the start of a new frame of data. This signal will only be active for the A1 word of
a frame.
Once frame synchronization has occurred and the IPC has responded with a FIFO enable signal, data will be writ-
ten into the memory. Only the payload (cells) is written to the FIFO. The TOH bytes are not written into the FIFO.
The cell octets immediately following the A1A2 bytes will be always written to the top of the FIFO.
Once a full cell has been written to the memory, the write control logic will send a control signal to the IPC8 or IPC2
block which will start the process of reading data from the FIFO. The IPC will read one whole cell at a time from
each of the 8 FIFO blocks, if congured for the eight-link cell mode or from each of 2 FIFO blocks if congured for
the two-link cell mode.
相关PDF资料 |
PDF描述 |
|---|---|
| M-ORSO82G52BM680-DB | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| M-ORT82G51BM680-DB | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| M-ORT82G52BM680-DB | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| M.PI-1R1D12 | 1 ELEMENT, 1.1 uH, GENERAL PURPOSE INDUCTOR, SMD |
| M01-014-1452PA | 14 CONTACT(S), MALE, RIGHT ANGLE TELECOM AND DATACOM CONNECTOR, SOLDER |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MORTAR-44LB | 制造商:3M Electronic Products Division 功能描述:3M(TM) FIRE BARRIER MORTAR, 44 98040056073 制造商:3M Electronic Products Division 功能描述:Fire Barrier 44 lb Bag |
| MO-RX3930 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FSK RECEIVER MODULE |
| MO-RX3930-FS | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FSK RECEIVER MODULE |
| MO-RX3930-FS315M | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FSK RECEIVER MODULE |
| MO-RX3930-FS434M | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FSK RECEIVER MODULE |
发布紧急采购，3分钟左右您将得到回复。