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| 型号： | M-ORSO82G51BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 65/123页 |
| 文件大小： | 2207K |
| 代理商： | M-ORSO82G51BM680-DB |
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Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
46
Cell Mode Detailed Description
A common application for the ORSO82G5 is to provide a bridge between a port card and a cell-based switch fabric.
In cell mode, the data in the Synchronous Payload Envelope (SPE) of the SONET frames is further formatted into
xed-length cells by the ORSO82G5. The cell contents will typically be unique to specic port card and switch
devices. The ORSO82G5 supports this application with a "cell mode" of operation
The basic data ows in cell mode are shown in Table 31. Data to be transmitted is received from the FPGA logic
(see Table 9 for details of the core/FPGA signal assignments which differ signicantly from the SERDES only and
SONET modes), inserted into the SPE of the SONET frame, scrambled and transmitted from the SERDES block.
In cell mode, multiple SERDES links are used to achieve desired bandwidth. Both two-link and eight-link cell
modes are supported. For such interfaces, data are cell-striped in a round-robin fashion across multiple links by the
transmitter.
Figure 31. Basic Data Flows - Cell Mode
In the receive direction, the framed data are received from the SERDES block, descrambled and are passed into a
cell extractor which extracts individual cells from the payload portion of the SONET frame. The cells are then
passed through a FIFO that performs lane-to-lane deskew and a clock domain transfer. The clock domain transfer
is handled automatically using idle cell insertion and deletion.
The cells are passed into either the eight-link Input Port Controller IPC8 block or to one of the four two-link
IPC2_[A:B][1:2] block(s) which reassemble the cells back into a single cell stream (destriping) which is sent to the
FPGA logic. (See Table 10 for details of the core/FPGA signal assignments. As with the transmit path, the cell
mode assignments differ signicantly from those for the SERDES only and SONET modes).
SERDES and SONET processing has been described in previous sections and only features unique to the cell
mode will be discussed in the following sections. The cell format will be discussed rst, followed by a description of
the transmit path, which will include either a two-link or an eight-link Output Port Controller (OPC) block, and a
description of the receive path, including the two-link or eight-link Input Port Controller (IPC) blocks.
Cell Formats
Cells are arranged within a SONET (STS-48c) frame as shown in Figure 32. A SONET STS-48c frame has 4176
(87 x 48) columns of SPE and 9 rows that gives a total of 37,584 bytes. In this implementation, data in a SPE is lim-
ited to xed size cells. Though four cell sizes are supported, only one cell size can be used at a time.
Receive (RX) Path
Transmit (TX) Path
Cell
Processing
Pseudo-
SONET
Processing
MUX/DEMUX
&
SERDES
ORCA 4E04
FPGA
Logic
Configurable
as
8
data
channels
Organized
in
two
four
channel
blocks
(quads)
User
Configurab
le
I/O
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