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| 型号： | M-ORSO82G51BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 111/123页 |
| 文件大小： | 2207K |
| 代理商： | M-ORSO82G51BM680-DB |
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Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
88
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-
lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operations sections of this data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
The ORCA Series 4 FPSCs include circuitry designed to protect the chips from damaging substrate injection cur-
rents and to prevent accumulations of static charge. Nevertheless, conventional precautions should be observed
during storage, handling, and use to avoid exposure to excessive electrical stress.
Table 23. Absolute Maximum Ratings
Recommended Operating Conditions
Table 24. Recommended Operating Conditions
*For FPGA Recommended Operating Conditions and Electrical Characteristics, see Recommended Operating Conditions and Electrical Char-
acteristics tables in the Series 4 FPGA Data Sheet and the Series 4 I/O Buffer Application Note. FPSC Standby Currents (IDDSB15 and
IDD
SB33 are tested with the Embedded Core in the powered down state
Designed for greater than 10 year electromigration life at 3.125 Gbits/s at 100 C junction temperature.
Note: VDDIB is the center tap of the CML input buffer. In some cases this signal may be left oating, or tied to another voltage level when not
interfacing to CML output buffers. See the SERDES CML Buffer Interface Technical Note for details.
SERDES Electrical and Timing Characteristics
Table 25. Maximum Power Dissipation
Parameter
Symbol
Min
Max
Unit
Storage Temperature
Tstg
– 65
150
°C
Power Supply Voltage with Respect to Ground
VDD33
– 0.3
4.2
V
VDDIO
– 0.3
4.2
V
VDD15
– 0.3
2.0
V
Input Signal with Respect to Ground
VIN
VSS – 0.3
VDDIO + 0.3
V
Signal Applied to High-impedance Output
—
VSS – 0.3
VDDIO + 0.3
V
Maximum Package Body (Soldering) Temperature
—
220
°C
Parameter
Symbol
Min
Max
Unit
Power Supply Voltage with Respect to Ground*
VDD33
3.0
3.6
V
VDD15
1.425
1.575
V
Input Voltages
VIN
VSS – 0.3
VDDIO + 0.3
V
Junction Temperature
TJ
– 40
125
°C
SERDES VDD15 Supply Voltage (VDDRx, VDDTx, VDDAUX, VDDGB)
1.425
1.575
V
SERDES CML I/O Supply Voltage (VDDIB, VDDOB)
1.425
1.890
V
Parameter
Conditions
Min
Typ
Max
Unit
Power Dissipation
SERDES, MUX/DEMUX, Align FIFO, and I/O (per channel) 1.25 Gbits/s
—
195
mW
SERDES, MUX/DEMUX, Align FIFO, and I/O (per channel) 2.5 Gbits/s
225
mW
Scrambler and Cell Processing Logic (per channel)
—
50
mW
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