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| 型号： | M-ORSO82G51BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 95/123页 |
| 文件大小： | 2207K |
| 代理商： | M-ORSO82G51BM680-DB |
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Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
73
Table 19. Per-Channel Control Register Descriptions
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
Mode
30800 - AA
30810 - AB
30820 - AC
30830 - AD
30900 - BA
30910 - BB
30920 - BC
30930 - BD
[0:4]
RSVD
00
Reserved
[5]
CELL_ALIGN_ERR_EN_xx
Cell Alignment Error, CELL_ALIGN_ERR = 1
indicates that the internal transmit frame pro-
cessor did not detect a start of cell indicator
when it was expecting a new cell. If the corre-
sponding alarm enable bit has been set, a 1 on
this bit will cause an alarm.
Cell
[6]
TX_URUN_ERR_EN_xx
Transmit Underrun Error, TX_URUN_ERR = 1
indicates an underrun error in the transmit
Asynchronous FIFO. If the corresponding alarm
enable bit has been set, a 1 on this bit will
cause an alarm.
Cell
[7]
TX_ORUN_ERR_EN_xx
Transmit Overrun Error, TX_ORUN_ERR = 1
indicates an overrun error in the transmit Asyn-
chronous FIFO. The TX FIFO is designed to not
overow since it sends backpressure signal to
the FPGA when it cannot accept more cells. If
the corresponding alarm enable bit has been
set, a 1 on this bit will cause an alarm.
Cell
30801 - AA
30811 - AB
30821 - AC
30831 - AD
30901 - BA
30911 - BB
30921 - BC
30931 - BD
[0]
RSVD
00
Reserved
[1]
OOF_EN_xx
Out of Frame, OOF_xx = 1 indicates OOF has
been detected in this link. If the corresponding
alarm enable bit has been set, a 1 on this bit
will cause an alarm.
Both
[2]
EX_SEQ_ERR_EN_xx
Excessive Sequence Errors, EX_SEQ_ERR =
1 indicates that three consecutive cells contain-
ing sequence errors have been detected in this
link. If the corresponding alarm enable bit has
been set, a 1 on this bit will cause an alarm.
Cell
[3]
SEQ_ERR_EN_xx
Sequence Error, SEQ_ERR = 1 indicates that a
sequence error has been detected for a cell on
this link. If the corresponding alarm enable bit
has been set, a 1 on this bit will cause an
alarm.
Cell
[4]
CELL_BIP_ERR_EN_xx
‘1’ = Alarm enabled for CELL_BIP_ERR_xx
Cell
[5]
B1_ERR_EN_xx
‘1’ = Alarm enabled for B1_ERR_xx
Both
[6]
RX_FIFO_OVRUN_EN_xx
‘1’ = Alarm enabled for RX_FIFO_OVRUN_xx
Cell
[7]
RDI_EN_xx
’1’ = Alarm enabled for RDI_xx
Both
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