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| 型号： | M-ORSO82G51BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 43/123页 |
| 文件大小： | 2207K |
| 代理商： | M-ORSO82G51BM680-DB |
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Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
26
SONET Mode Operation - Detailed Description
The following sections describe the data processing performed in the SONET logic blocks. The basic data ows in
the SONET Mode are shown in Figure 13. At a top level, the descriptions are separated into processing in the
transmit path (FPGA to serial link) and processing in the receive path (serial link to FPGA). In general, the descrip-
tions in the next sections are written to describe SONET mode operation, although some of the "SONET logic
blocks" are also used in cell mode operation. The various processing options are selected by setting bits in control
registers and status information is written to status registers. Both types of registers can be written and/or read
from the System Bus and the MicroProcessor Interface (MPI). Memory maps and descriptions for the registers are
Figure 13. Basic Data Flows - SONET Mode
In the SONET mode, the transmit block receives 32-bit wide data from the FPGA (DINxx) on each of its 8 channels
along with a frame pulse (DINxx_FP) per channel and a transmit clock (TSYCLKxx). See Table 9 for details of the
core/FPGA signal assignments. Typically this will represent a STS-48 stream on each link. The data are rst
passed through a TOH block which will generate all the timing pulses that are required to isolate individual over-
head bytes (e.g., A1, A2, B1, D1-D3 etc.). The timing pulse generation will be based on the system frame pulse
(DINxx_FP) received from the FPGA logic, hence it is recommended that, for multi-channel alignment at the
receiver, the frame pulses for the channels in an alignment group be synchronized. The data are then scrambled
before being sent to the SERDES.
In the receive direction, each of the two SONET quads process four receiving channels which can be treated as
one STS-192 stream or as four independent STS-48 streams.The clocks for the received data are recovered from
the received serial data streams and a serial to parallel conversion is performed on the data. The frame format of
the incoming data are reconstructed (optional). The data then is descrambled using the standard STS-12 polyno-
mial and a B1 parity error check is performed on the data from the previously transmitted frame.
In the SONET mode, the incoming serial data streams can be aligned by groups of two, four or eight. When doing
multichannel alignment of two or more data streams, the receiver can handle the data streams with frame offsets of
up to 18 bytes due to timing skews between cards and along backplane traces or other transmission medium. For
multichannel alignment capability to operate properly, it should be noted that while the skew between channels can
be very large, they must operate at the exact same frequency (0 ppm frequency deviation), thus requiring that the
transmitters sourcing the data being received be driven by the same clock source. It is highly recommended that
the frame pulses, DINxx_FP, for all links in an alignment group be synchronized. (See Table 9 for details of the
core/FPGA transmit direction signal assignments.)
Receive (RX) Path
Transmit (TX) Path
Cell
Processing
Pseudo-
SONET
Processing
MUX/DEMUX
&
SERDES
ORCA 4E04
FPGA
Logic
Configurable
as
8
data
channels
Organized
in
two
four
channel
blocks
(quads)
User
Configurab
le
I/O
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