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| 型号： | M-ORSO82G51BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 13/123页 |
| 文件大小： | 2207K |
| 代理商： | M-ORSO82G51BM680-DB |
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Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
11
ORSO82G5 Overview
The ORSO82G5 FPSC provides high-speed backplane transceivers combined with FPGA logic. The ORSO82G5
device is based on the 1.5 V OR4E04 ORCA FPGA and has a 36 x 36 array of Programmable Logic Cells (PLCs).
The embedded core which contains the backplane transceivers is attached to the right side of the device and is
integrated directly into the FPGA array. A top level diagram of the basic chip conguration is shown in Figure 1
Figure 1. ORSO82G5 Basic Chip Conguration
The ORSO82G5 supports aggregate bandwidths up to 21.6 Gbits/s and is targeted towards users needing high-
speed backplane interfaces for SONET and other non-SONET proprietary backplanes. For non-SONET applica-
tions, all SONET functionality is hidden from the user and no prior networking knowledge is required.
Built using Series 4 recongurable System-on-a-Chip (SoC) architecture, the ORSO82G5 contains the FPGA base
array and an embedded core supporting eight serial data channels, with clock and data recovery functions, and
provides SONET framing, scrambling/descrambling and cell processing on a single monolithic chip and enables
high-speed asynchronous serial data transfer between system devices. Devices can be on the same PC-board, on
separate boards connected across a backplane or connected by cables. The ORSO82G5 is completely pin-com-
patible with the ORT82G5 device.
The ORSO82G5 is considered a pseudo-SONET device because it does not support full overhead processing,
pointer processing or meet all SONET jitter/timing requirements. The ORSO82G5 is designed primarily for use as
a SONET backplane device and not for network termination. Although it formats and processes data as SONET
frames, because the embedded core is not fully SONET compliant on a stand-alone basis, it can not terminate data
directly on a SONET ring without additional functionality being implemented in the FPGA logic.
The ORSO82G5 embedded core does support the following:
Section/Line Overhead: A1/A2 (framing bytes), B1 (BIP-8), K2 (APS)
Alarms: OOF (Out Of Frame), B1 error, RDI
Automatic Transport OverHead (TOH) generation and insertion
AIS-L insertion
SPE signal generation which support +/- stuff events (but no pointer processing)
Embedded
Serial
I/O
Core
(8 Serial
Channels)
ORCA 4E04-Based
Programmable Logic
FPGA
I/O
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