参数资料
型号: W631GG6KB-15
厂商: Winbond Electronics
文件页数: 106/159页
文件大小: 0K
描述: IC DDR3 SDRAM 1GBIT 96WBGA
标准包装: 200
格式 - 存储器: RAM
存储器类型: DDR3 SDRAM
存储容量: 1G(64M x 16)
速度: 667MHz
接口: 并联
电源电压: 1.425 V ~ 1.575 V
工作温度: 0°C ~ 85°C
封装/外壳: 96-TFBGA
供应商设备封装: 96-WBGA(9x13)
包装: 托盘
W631GG6KB
Note:
1. Extended range for V IX is only allowed for clock and if single-ended clock input signals CK and CK# are monotonic with a
single-ended swing V SEL /V SEH of at least V DD /2 ± 250 mV, and when the differential slew rate of CK - CK# is larger
than 3 V/nS. Refer to Table 21 for V SEL and V SEH standard values.
2. The relation between V IX Min/Max and V SEL /V SEH should satisfy following.
(V DD /2) + V IX (Min) - VSEL ≥ 25mV
V SEH - ((V DD /2) + V IX (Max)) ≥ 25mV
10.6.6 Slew Rate Definitions for Single-Ended Input Signals
See section 10.16.4 “ Address / Command Setup, Hold and Derating ” on page 149 for single-
ended slew rate definitions for address and command signals.
See section 10.16.5 “ Data Setup, Hold and Slew Rate Derating ” on page 156 for single-ended slew
rate definitions for data signals.
10.6.7 Slew Rate Definitions for Differential Input Signals
Input slew rate for differential signals (CK, CK# and DQS, DQS#) are defined and measured as shown
in Table 23 and Figure 93.
Table 23 – Differential Input Slew Rate Definition
Description
Measured
from
to
Defined by
Differential input slew rate for rising edge
(CK - CK# and DQS - DQS#)
Differential input slew rate for falling edge
(CK - CK# and DQS - DQS#)
V IL.DIFFmax
V IH.DIFFmin
V IH.DIFFmin
V IL.DIFFmax
[V IH.DIFFmin - V IL.DIFFmax ] / Δ TR. DIFF
[V IH.DIFFmin - V IL.DIFFmax ] / Δ TF. DIFF
Note: The differential signal (i.e., CK - CK# and DQS - DQS#) must be linear between these thresholds
Δ TR. DIFF
V IH.DIFF min
0
V IL.DIFF max
Δ TF. DIFF
Figure 93 – Differential Input Slew Rate Definition for DQS, DQS# and CK, CK#
Publication Release Date: Dec. 09, 2013
Revision A05
- 106 -
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