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参数资料
型号： W631GG6KB-15
厂商： Winbond Electronics
文件页数： 79/159页
文件大小： 0K
描述： IC DDR3 SDRAM 1GBIT 96WBGA
标准包装： 200
格式 - 存储器： RAM
存储器类型： DDR3 SDRAM
存储容量： 1G（64M x 16）
速度： 667MHz
接口： 并联
电源电压： 1.425 V ~ 1.575 V
工作温度： 0°C ~ 85°C
封装/外壳： 96-TFBGA
供应商设备封装： 96-WBGA（9x13）
包装： 托盘
W631GG6KB
8.19 On-Die Termination (ODT)
ODT (On-Die Termination) is a feature of the DDR3 SDRAM that allows the DRAM to turn on/off
termination resistance for each DQU, DQL, DQSU, DQSU#, DQSL, DQSL#, DMU and DML signal via
the ODT control pin. The ODT feature is designed to improve signal integrity of the memory channel
by allowing the DRAM controller to independently turn on/off termination resistance for any or all
DRAM devices. More details about ODT control modes and ODT timing modes can be found further
down in this document:
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The ODT control modes are described in section 8.19.1
The ODT synchronous mode is described in section 8.19.2
The dynamic ODT feature is described in section 8.19.3
The ODT asynchronous mode is described in section 8.19.4
The transitions between ODT synchronous and asynchronous are described in section 8.19.4.1
through section 8.19.4.4
The ODT feature is turned off and not supported in Self-Refresh mode.
A simple functional representation of the DRAM ODT feature is shown in Figure 73.
To other
circuitry
ODT
V DDQ / 2
R TT
like
Swtich
RCV, …
DQ, DQS, DM
Figure 73 – Functional Representation of ODT
The switch is enabled by the internal ODT control logic, which uses the external ODT pin and other
control information, see below. The value of R TT is determined by the settings of Mode Register bits
(see Figure 6 - MR1 Definition on page 20 and Figure 7 - MR2 Definition on page 22). The ODT pin
will be ignored if the Mode Registers MR1 and MR2 are programmed to disable ODT, and in self-
refresh mode.
8.19.1 ODT Mode Register and ODT Truth Table
The ODT Mode is enabled if any of MR1 {A9, A6, A2} or MR2 {A10, A9} are non zero. In this case, the
value of R TT is determined by the settings of those bits (see Figure 6 - MR1 Definition on page 20).
Application: Controller sends WR command together with ODT asserted.
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One possible application: The rank that is being written to provides termination.
DRAM turns ON termination if it sees ODT asserted (unless ODT is disabled by MR).
DRAM does not use any write or read command decode information.
The Termination Truth Table is shown in Table 8.
Table 8 – Termination Truth Table
ODT pin
0
1
DRAM Termination State
OFF
ON, (OFF, if disabled by MR1 {A9, A6, A2} and MR2 {A10, A9} in general)
Publication Release Date: Dec. 09, 2013
Revision A05
- 79 -
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