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参数资料
型号： W631GG6KB-15
厂商： Winbond Electronics
文件页数： 141/159页
文件大小： 0K
描述： IC DDR3 SDRAM 1GBIT 96WBGA
标准包装： 200
格式 - 存储器： RAM
存储器类型： DDR3 SDRAM
存储容量： 1G（64M x 16）
速度： 667MHz
接口： 并联
电源电压： 1.425 V ~ 1.575 V
工作温度： 0°C ~ 85°C
封装/外壳： 96-TFBGA
供应商设备封装： 96-WBGA（9x13）
包装： 托盘
W631GG6KB
AC Timing and Operating Condition for -11 speed grade, continued
SYMBOL
SPEED GRADE
PARAMETER
MIN.
DDR3-1866 (-11)
MAX.
UNITS NOTES
Power Down Timing
t XP
Exit Power Down with DLL on to any valid
command; Exit Precharge Power Down with DLL
max(3nCK, 6nS)
?
34
frozen to commands not requiring a locked DLL
t XPDLL
t CKE
t CPDED
t PD
Exit Precharge Power Down with DLL frozen to
commands requiring a locked DLL
CKE minimum pulse width
Command pass disable delay
Power Down Entry to Exit Timing
max(10nCK, 24nS)
max(3nCK, 5nS)
2
t CKE (min)
?
?
?
9 * t REFI
nCK
35
25
t ACTPDEN Timing of ACT command to Power Down entry
1
?
nCK
27
t PRPDEN
t RDPDEN
Timing of PRE or PREA command to Power Down
entry
Timing of RD/RDA command to Power Down entry
1
RL + 4 + 1
?
?
nCK
nCK
27
t WRPDEN
Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
Min.: WL + 4 + roundup (t WR (min)/ t CK (avg))
Max.: ?
nCK
20
t WRAPDEN
Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
Min.: WL + 4 +
Max.: ?
WR + 1
nCK
19
t WRPDEN
Timing of WR command to Power Down entry
(BC4MRS)
Min.: WL + 2 + roundup (t WR (min)/ t CK (avg))
Max.: ?
nCK
20
t WRAPDEN
Timing of WRA command to Power Down entry
(BC4MRS)
Min.: WL + 2 +
Max.: ?
WR + 1
nCK
19
t REFPDEN Timing of REF command to Power Down entry
t MRSPDEN Timing of MRS command to Power Down entry
1
t MOD (min)
?
?
nCK
27, 28
ODT Timing
ODTH4
ODTH8
t AONPD
t AOFPD
t AON
ODT high time without write command or with write
command and burst chop 4
ODT high time with Write command and burst
length 8
Asynchronous R TT turn-on delay (Power Down
with DLL frozen)
Asynchronous R TT turn-off delay (Power Down
with DLL frozen)
R TT turn-on
4
6
2
2
-195
?
?
8.5
8.5
195
nCK
nCK
nS
nS
pS
30
31
32
32
17, 43
t AOF
Rtt_Nom and Rtt_WR turn-off time from ODTLoff
reference
0.3
0.7
t CK (avg) 17, 44
t ADC
R TT dynamic change skew
0.3
0.7
t CK (avg)
17
Write Leveling Timing
t WLMRD
t WLDQSEN
t WLS
t WLH
t WLO
t WLOE
First DQS/DQS# rising edge after write leveling
mode is programmed
DQS/DQS# delay after write leveling mode is
programmed
Write leveling setup time from (CK, CK#) zero
crossing to rising (DQS, DQS#) zero crossing
Write leveling hold time from rising (DQS, DQS#)
zero crossing to (CK, CK#) zero crossing
Write leveling output delay
Write leveling output error
40
25
140
140
0
0
?
?
?
?
7.5
2
nCK
nCK
pS
pS
nS
nS
5
5
Publication Release Date: Dec. 09, 2013
Revision A05
- 141 -
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