参数资料
型号: W631GG6KB-15
厂商: Winbond Electronics
文件页数: 115/159页
文件大小: 0K
描述: IC DDR3 SDRAM 1GBIT 96WBGA
标准包装: 200
格式 - 存储器: RAM
存储器类型: DDR3 SDRAM
存储容量: 1G(64M x 16)
速度: 667MHz
接口: 并联
电源电压: 1.425 V ~ 1.575 V
工作温度: 0°C ~ 85°C
封装/外壳: 96-TFBGA
供应商设备封装: 96-WBGA(9x13)
包装: 托盘
W631GG6KB
10.9.4 Design guide lines for R TT PU and R TT PD
Table 35 provides an overview of the ODT DC electrical pull-up and pull-down characteristics. The
values are not specification requirements, but can be used as design guide lines.
Table 35 – ODT DC Electrical Pull-Down and Pull-Up Characteristics, assuming R ZQ = 240 Ω ± 1%
entire operating temperature range; after proper ZQ calibration
MR1 A9, A6, A2
R TT
Resistor
V out
Min.
Nom.
Max.
Unit
Notes
0, 1, 0
120 Ω, R TT 120PD240 ,
V OLDC = 0.2 × V DDQ
0.6
1.0
1.1
R ZQ /TISF PUPD
1, 2, 3, 4, 5
0, 0, 1
0, 1, 1
60 Ω,
40 Ω,
R TT 60PD120 ,
R TT 40PD80 ,
V OMDC = 0.5 × V DDQ
V OHDC = 0.8 × V DDQ
0.9
0.9
1.0
1.0
1.1
1.4
R ZQ /TISF PUPD
R ZQ /TISF PUPD
1, 2, 3, 4, 5
1, 2, 3, 4, 5
1, 0, 1
1, 0, 0
30 Ω,
20 Ω
R TT 30PD60 ,
R TT 20PD40
R TT 120PU240 ,
R TT 60PU120 ,
R TT 40PU80 ,
V OLDC = 0.2 × V DDQ
V OMDC = 0.5 × V DDQ
V OHDC = 0.8 × V DDQ
0.9
0.9
0.6
1.0
1.0
1.0
1.4
1.1
1.1
R ZQ /TISF PUPD
R ZQ /TISF PUPD
R ZQ /TISF PUPD
1, 2, 3, 4, 5
1, 2, 3, 4, 5
1, 2, 3, 4, 5
R TT 30PU60 ,
R TT 20PU40
Notes:
1. TISF PUPD : Termination Impedance Scaling Factor for Pull-Up and Pull-Down path:
TISF PUPD = 1 for R TT 120PU/PD240
TISF PUPD = 2 for R TT 60PU/PD120
TISF PUPD = 3 for R TT 40PU/PD80
TISF PUPD = 4 for R TT 30PU/PD60
TISF PUPD = 6 for R TT 20PU/PD40
2. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance
limits if temperature or voltage changes after calibration, see the above section ODT temperature and voltage sensitivity.
3. The tolerance limits are specified under the condition that V DDQ = V DD and that V SSQ = V SS .
4. Pull-down and pull-up ODT resistors are recommended to be calibrated at 0.5 × V DDQ . Other calibration schemes may be
used to achieve the linearity spec shown above, e.g. calibration at 0.2 × V DDQ and 0.8 × V DDQ .
5. Not a specification requirement, but a design guide line.
Publication Release Date: Dec. 09, 2013
Revision A05
- 115 -
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