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| 型号： | W631GG6KB-15 |
| 厂商： | Winbond Electronics |
| 文件页数： | 149/159页 |
| 文件大小： | 0K |
| 描述： | IC DDR3 SDRAM 1GBIT 96WBGA |
| 标准包装： | 200 |
| 格式 - 存储器： | RAM |
| 存储器类型： | DDR3 SDRAM |
| 存储容量： | 1G（64M x 16） |
| 速度： | 667MHz |
| 接口： | 并联 |
| 电源电压： | 1.425 V ~ 1.575 V |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 96-TFBGA |
| 供应商设备封装： | 96-WBGA（9x13） |
| 包装： | 托盘 |
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W631GG6KB
10.16.4 Address / Command Setup, Hold and Derating
For all input signals the total t IS (setup time) and t IH (hold time) required is calculated by adding the
datasheet t IS(base) and t IH(base) value (see Table 48 ) to the Δt IS and Δt IH derating value (see Table 49
to Table 52) respectively. Example: t IS (total setup time) = t IS(base) + Δt IS
Setup (t IS ) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
V REF(DC) and the first crossing of V IH(AC) min. Setup (t IS ) nominal slew rate for a falling signal is
defined as the slew rate between the last crossing of V REF(DC) and the first crossing of V IL(AC) max. If
the actual signal is always earlier than the nominal slew rate line between shaded ?V REF(DC) to AC
region‘, use nominal slew rate for derating value (see Figure 107). If the actual signal is later than the
nominal slew rate line anywhere between shaded ?V REF(DC) to AC region‘, the slew rate of a tangent
line to the actual signal from the AC level to V REF(DC) level is used for derating value (see Figure 109).
Hold (t IH ) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
V IL(DC) max and the first crossing of V REF(DC) . Hold (t IH ) nominal slew rate for a falling signal is defined
as the slew rate between the last crossing of V IH(DC) min and the first crossing of V REF(DC) . If the actual
signal is always later than the nominal slew rate line between shaded ?DC to V REF(DC) region‘, use
nominal slew rate for derating value (see Figure 108). If the actual signal is earlier than the nominal
slew rate line anywhere between shaded ?DC to V REF(DC) region‘, the slew rate of a tangent line to the
actual signal from the DC level to V REF(DC) level is used for derating value (see Figure 110).
For a valid transition the input signal has to remain above/below V IH/IL(AC) for some time t VAC (see
Table 53).
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not
have reached V IH/IL(AC) at the time of the rising clock transition, a valid input signal is still required to
complete the transition and reach V IH/IL(AC) .
For slew rates in between the values listed in the tables, the derating values may obtained by linear
interpolation.
These values are typically not subject to production test. They are verified by design and
characterization.
Table 48 – ADD/CMD Setup and Hold Base-Values for 1V/nS
Symbol
t IS(base) AC175
t IS(base) AC150
t IS(base) AC135
t IS(base) AC125
t IH(base) DC100
Reference
V IH/L(AC)
V IH/L(AC)
V IH/L(AC)
V IH/L(AC)
V IH/L(DC)
DDR3-1333
65
190
-
-
140
DDR3-1600
45
170
-
-
120
DDR3-1866
-
-
65
150
100
Unit
pS
pS
pS
pS
pS
Notes:
1. (AC/DC referenced for 1V/nS Address/Command slew rate and 2 V/nS differential CK-CK# slew rate)
2. The t IS(base) AC150 specifications are adjusted from the t IS(base) AC175 specification by adding an additional 100pS for
DDR3-1333/1600 of derating to accommodate for the lower alternate threshold of 150 mV and another 25 pS to account for
the earlier reference point [(175 mV - 150 mV) / 1 V/nS].
3. The t IS(base) AC125 specifications are adjusted from the t IS(base) AC135 specification by adding an additional 75pS for
DDR3-1866 of derating to accommodate for the lower alternate threshold of 125 mV and another 10 pS to account for the
earlier reference point [(135 mV - 125 mV) / 1 V/nS].
Publication Release Date: Dec. 09, 2013
Revision A05
- 149 -
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