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型号： W631GG6KB-15
厂商： Winbond Electronics
文件页数： 27/159页
文件大小： 0K
描述： IC DDR3 SDRAM 1GBIT 96WBGA
标准包装： 200
格式 - 存储器： RAM
存储器类型： DDR3 SDRAM
存储容量： 1G（64M x 16）
速度： 667MHz
接口： 并联
电源电压： 1.425 V ~ 1.575 V
工作温度： 0°C ~ 85°C
封装/外壳： 96-TFBGA
供应商设备封装： 96-WBGA（9x13）
包装： 托盘
W631GG6KB
8.7.2
DLL “off” to DLL “on” Procedure
To switch from DLL ―off‖ to DLL ―on‖ (with required frequency change) during Self -Refresh:
1. Starting from Idle state (All banks pre-charged, all timings fulfilled and DRAMs On-die Termination
resistors (R TT ) must be in high impedance state before Self-Refresh mode is entered.)
2. Enter Self Refresh Mode, wait until t CKSRE satisfied.
3. Change frequency, in guidance with section 8.8 “ Input clock frequency change ” on page 28.
4. Wait until a stable clock is available for at least (t CKSRX ) at DRAM inputs.
5. Starting with the Self Refresh Exit command, CKE must continuously be registered HIGH until
t DLLK timing from subsequent DLL Reset command is satisfied. In addition, if any ODT features
were enabled in the mode registers when Self Refresh mode was entered, the ODT signal must
continuously be registered LOW until t DLLK timings from subsequent DLL Reset command is
satisfied. If both ODT features are disabled in the mode registers when Self Refresh mode was
entered, ODT signal can be registered LOW or HIGH.
6. Wait t XS , then set MR1 bit A0 to ―0‖ to enable the DLL.
7. Wait t MRD , then set MR0 bit A8 to ―1‖ to start DLL Reset .
8. Wait t MRD , then set Mode Registers with appropriate values (especially an update of CL, CWL and
WR may be necessary. After t MOD satisfied from any proceeding MRS command, a ZQCL
command may also be issued during or after t DLLK .)
9. Wait for t MOD , then DRAM is ready for next command (Remember to wait t DLLK after DLL Reset
before applying command requiring a locked DLL!). In addition, wait also for t ZQ oper in case a
ZQCL command was issued.
T0
Ta0
Ta1
Tb0
Tc0
Tc1
Td0
Te0
Tf1
Tg0
Th0
CK#
CK
CKE
t DLLK
VALID
Command
NOP
SRE *2
NOP
SRX *5
MRS *6
MRS *7
MRS *8
VALID *9
*1
ODTLoff + 1 x t CK
t CKSRE
*3
t CKSRX *4
t XS
t MRD
t MRD
t CKESR
ODT
ODT: Static LOW in case Rtt_Nom and Rtt_WR is enabled, otherwise static Low or High
Notes:
1. Starting with idle state
2. Enter SR
TIME BREAK
DON'T CARE
3. Change Frequency
4. Clock must be stable t CKSRX
5. Exit SR
6. Set DLL on by MR1 A0 = 0
7. Update Mode registers
8. Any valid command
Figure 11 – DLL Switch Sequence from DLL Off to DLL On
Publication Release Date: Dec. 09, 2013
Revision A05
- 27 -
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