参数资料
型号: W631GG6KB-15
厂商: Winbond Electronics
文件页数: 22/159页
文件大小: 0K
描述: IC DDR3 SDRAM 1GBIT 96WBGA
标准包装: 200
格式 - 存储器: RAM
存储器类型: DDR3 SDRAM
存储容量: 1G(64M x 16)
速度: 667MHz
接口: 并联
电源电压: 1.425 V ~ 1.575 V
工作温度: 0°C ~ 85°C
封装/外壳: 96-TFBGA
供应商设备封装: 96-WBGA(9x13)
包装: 托盘
W631GG6KB
8.3.3
Mode Register MR2
The Mode Register MR2 stores the data for controlling refresh related features, Rtt_WR impedance,
and CAS write latency. The Mode Register 2 is written by asserting low on CS#, RAS#, CAS#, WE#,
high on BA1 and low on BA0 and BA2, while controlling the states of address pins according to the
Figure 7 below.
BA2
BA1
BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Field
0 * 1
1
0
0 * 1
Rtt_WR
0 * 1
SRT
ASR
CWL
PASR
Mode Register 2
BA1
0
BA0
0
MR Select
MR0
A2
0
A1
0
A0
0
Partial Array Self Refresh for 8 Banks
Full array
0
1
MR1
1
1
0
1
MR2
MR3
0
0
0
1
1
0
Half Array (BA[2:0]=000,001,010 & 011)
Quarter Array (BA[2:0]=000 & 001)
A6
0
1
A7
0
Auto Self Refresh (ASR)
Manual SR Reference (SRT)
ASR enable
Self Refresh Temperature (SRT) Range
Normal operating temperature range
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
1/8th Array (BA[2:0]=000)
3/4 Array (BA[2:0]=010,011,100,101,110 & 111)
Half Array (BA[2:0]=100,101,110 & 111)
Quarter Array (BA[2:0]=110 & 111)
1/8th Array (BA[2:0]=111)
1
Extended operating temperature range
A5
A4
A3
CAS write Latency (CWL)
A10
0
0
1
1
A9
0
1
0
1
Rtt_WR* 2
Dynamic ODT off
(Write does not affect Rtt value)
RZQ/4
RZQ/2
Reserved
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
5 (tCK(avg) ≥ 2.5nS)
6 (2.5nS > tCK(avg) ≥ 1.875nS)
7 (1.875nS > tCK(avg) ≥ 1.5nS)
8 (1.5nS > tCK(avg) ≥ 1.25nS)
9 (1.25nS > tCK(avg) ≥ 1.07nS)
1
1
1
0
1
1
1
0
1
Reserved
Reserved
Reserved
Notes:
1. BA2, A8, A11~A12 are reserved for future use and must be programmed to 0 during MRS.
2. The Rtt_WR value can be applied during writes even when Rtt_Nom is disabled. During write leveling, Dynamic ODT is not
available.
Figure 7 – MR2 Definition
Publication Release Date: Dec. 09, 2013
Revision A05
- 22 -
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