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型号： W631GG6KB-15
厂商： Winbond Electronics
文件页数： 89/159页
文件大小： 0K
描述： IC DDR3 SDRAM 1GBIT 96WBGA
标准包装： 200
格式 - 存储器： RAM
存储器类型： DDR3 SDRAM
存储容量： 1G（64M x 16）
速度： 667MHz
接口： 并联
电源电压： 1.425 V ~ 1.575 V
工作温度： 0°C ~ 85°C
封装/外壳： 96-TFBGA
供应商设备封装： 96-WBGA（9x13）
包装： 托盘
W631GG6KB
8.19.4.1 Synchronous to Asynchronous ODT Mode Transitions
Table 13 – ODT timing parameters for Power Down (with DLL frozen) entry and exit transition period
Description
ODT to R TT turn-
on delay
ODT to R TT turn-
off delay
Min.
min{ ODTLon * t CK(avg) + t AON min; t AONPD min }
min{ (WL - 2) * t CK(avg) + t AON min; t AONPD min }
min{ ODTLoff * t CK(avg) +t AOF min; t AOFPD min }
min{ (WL - 2) * t CK(avg) +t AOF min; t AOFPD min }
Max.
max{ ODTLon * t CK(avg) + t AON max; t AONPD max }
max{ (WL - 2) * t CK(avg) + t AON max; t AONPD max }
max{ ODTLoff * t CK(avg) + t AOF max; t AOFPD max }
max{ (WL - 2) * t CK(avg) + t AOF max; t AOFPD max }
t ANPD
WL -1
8.19.4.2 Synchronous to Asynchronous ODT Mode Transition during Power-Down Entry
If DLL is selected to be frozen in Precharge Power Down Mode by the setting of bit A12 in MR0 to ―0‖,
there is a transition period around power down entry, where the DDR3 SDRAM may show either
synchronous or asynchronous ODT behavior.
The transition period is defined by the parameters t ANPD and t CPDED (min). t ANPD is equal to (WL -1)
and is counted backwards in time from the clock cycle where CKE is first registered low. t CPDED (min)
starts with the clock cycle where CKE is first registered low. The transition period begins with the
starting point of t ANPD and terminates at the end point of t CPDED (min), as shown in Figure 83. If there
is a Refresh command in progress while CKE goes low, then the transition period ends at the later one
of t RFC (min) after the Refresh command and the end point of t CPDED (min), as shown in Figure 84.
Please note that the actual starting point at t ANPD is excluded from the transition period, and the actual
end points at t CPDED (min) and t RFC (min), respectively, are included in the transition period.
ODT assertion during the transition period may result in an R TT change as early as the smaller of
t AONPD min and (ODTLon*t CK(avg) + t AON min) and as late as the larger of t AONPD max and (ODTLon*
t CK(avg) + t AON max). ODT de-assertion during the transition period may result in an R TT change as
early as the smaller of t AOFPD min and (ODTLoff* t CK(avg) + t AOF min) and as late as the larger of
t AOFPD max and (ODTLoff* t CK(avg) + t AOF max). See Table 13.
Note that, if AL has a large value, the range where R TT is uncertain becomes quite large. Figure 83
shows the three different cases: ODT_A, synchronous behavior before t ANPD ; ODT_B has a state
change during the transition period; ODT_C shows a state change after the transition period.
Publication Release Date: Dec. 09, 2013
Revision A05
- 89 -
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