- 您现在的位置：买卖IC网 > Datasheet目录368 > W631GG6KB-15 (Winbond Electronics)IC DDR3 SDRAM 1GBIT 96WBGA Datasheet资料下载
参数资料
| 型号： | W631GG6KB-15 |
| 厂商： | Winbond Electronics |
| 文件页数： | 77/159页 |
| 文件大小： | 0K |
| 描述： | IC DDR3 SDRAM 1GBIT 96WBGA |
| 标准包装： | 200 |
| 格式 - 存储器： | RAM |
| 存储器类型： | DDR3 SDRAM |
| 存储容量： | 1G（64M x 16） |
| 速度： | 667MHz |
| 接口： | 并联 |
| 电源电压： | 1.425 V ~ 1.575 V |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 96-TFBGA |
| 供应商设备封装： | 96-WBGA（9x13） |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页当前第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页
W631GG6KB
8.18 ZQ Calibration Commands
8.18.1 ZQ Calibration Description
ZQ Calibration command is used to calibrate DRAM R ON & ODT values over PVT (process, voltage
and temperature). An external resistor (R ZQ ) between the DRAM ZQ pin and ground is used as a
calibration reference. DDR3 SDRAM needs longer time to calibrate output driver and on-die
termination circuits after power-up and/or any reset, medium time for a full calibration during normal
operation (e.g. after self-refresh exit) and relatively smaller time to perform periodic update calibrations.
ZQCL (ZQ Calibration Long) command is used to perform the initial calibration during power-up
initialization sequence. This command may be issued at any time by the controller depending on the
system environment. ZQCL command triggers the calibration engine inside the DRAM and, once
calibration is achieved, the calibrated values are transferred from the calibration engine to DRAM IO,
which gets reflected as updated output driver and on-die termination values.
The first ZQCL command issued after reset is allowed a timing period of t ZQ init to perform the full
calibration and the transfer of values. All other ZQCL commands except the first ZQCL command
issued after RESET are allowed a timing period of t ZQ oper.
ZQCS (ZQ Calibration Short) command is used to perform periodic calibrations to account for voltage
and temperature variations. A shorter timing window is provided to perform the calibration and transfer
of values as defined by timing parameter t ZQCS . One ZQCS command can effectively correct a
minimum of 0.5 % (ZQ Correction) of R ON and R TT impedance error within 64 nCK for all speed bins
assuming the maximum sensitivities specified in the ?Output Driver Voltage and Temperature
Sensitivity? and ?ODT Voltage and Temperature Sensitivity? tables. The appropriate interval
between ZQCS commands can be determined from these tables and other application-specific
parameters. One method for calculating the interval between ZQCS commands, given the temperature
(Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is subject to in the application, is
illustrated. The interval could be defined by the following formula:
ZQCorrecti on
(TSens × Tdriftrate ) + (VSens × Vdriftrate )
where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM
temperature and voltage sensitivities.
For example, if TSens = 1.5%/ ? C, VSens = 0.15%/mV, Tdriftrate = 1 ? C/sec and Vdriftrate = 15 mV/sec,
then the interval between ZQCS commands is calculated as:
0.5
(1.5 × 1) + (0.15 × 15)
= 0.133 ≈ 128mS
No other activities should be performed on the DRAM channel by the controller for the duration of
t ZQ init, t ZQ oper, or t ZQCS . The quiet time on the DRAM channel allows accurate calibration of output
driver and on-die termination values. Once DRAM calibration is achieved, the DRAM should disable
ZQ current consumption path to reduce power.
All banks must be precharged and t RP met before ZQCL or ZQCS commands are issued by the
controller. See section 9.1 “ Command Truth Table ” on Page 94 for a description of the ZQCL and
ZQCS commands.
ZQ calibration commands can also be issued in parallel to DLL lock time when coming out of self
refresh. Upon Self-Refresh exit, DDR3 SDRAM will not perform an IO calibration without an explicit
ZQ calibration command. The earliest possible time for ZQ Calibration command (ZQCS or ZQCL)
after self refresh exit is t XS .
In systems that share the ZQ resistor between devices, the controller must not allow any overlap of
t ZQ oper, t ZQ init, or t ZQCS between the devices.
Publication Release Date: Dec. 09, 2013
Revision A05
- 77 -
相关PDF资料 |
PDF描述 |
|---|---|
| W9412G6IH-5 | IC DDR-400 SDRAM 128MB 66TSSOPII |
| W9412G6JH-5I | IC DDR SDRAM 128MBIT 66TSOPII |
| W9425G6EH-5 | IC DDR-400 SDRAM 256MB 66TSSOPII |
| W9425G6JH-5I | IC DDR SDRAM 256MBIT 66TSOPII |
| W947D2HBJX5E | IC LPDDR SDRAM 128MBIT 90VFBGA |
相关代理商/技术参数 |
参数描述 |
|---|---|
| W631GG8KB-11 | 制造商:Winbond Electronics Corp 功能描述:IC DDR3 SDRAM 1GBIT 制造商:Winbond Electronics Corp 功能描述:IC DDR3 SDRAM 1GBIT 78WBGA |
| W631GG8KB-12 | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR3 SDRAM 1G-Bit 128Mx8 1.5V 制造商:Winbond Electronics Corp 功能描述:IC DDR3 SDRAM 1GBIT 制造商:Winbond Electronics Corp 功能描述:IC DDR3 SDRAM 1GBIT 78WBGA |
| W631GG8KB-15 | 制造商:Winbond Electronics Corp 功能描述:IC DDR3 SDRAM 1GBIT 制造商:Winbond Electronics Corp 功能描述:IC DDR3 SDRAM 1GBIT 78WBGA |
| W632 | 制造商:LUMINIS 制造商全称:LUMINIS 功能描述:Wall mount |
| W632GG6KB-11 | 制造商:Winbond Electronics Corp 功能描述:IC DDR3 SDRAM 2GBIT 96WBGA |
发布紧急采购，3分钟左右您将得到回复。