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型号： W631GG6KB-15
厂商： Winbond Electronics
文件页数： 156/159页
文件大小： 0K
描述： IC DDR3 SDRAM 1GBIT 96WBGA
标准包装： 200
格式 - 存储器： RAM
存储器类型： DDR3 SDRAM
存储容量： 1G（64M x 16）
速度： 667MHz
接口： 并联
电源电压： 1.425 V ~ 1.575 V
工作温度： 0°C ~ 85°C
封装/外壳： 96-TFBGA
供应商设备封装： 96-WBGA（9x13）
包装： 托盘
W631GG6KB
10.16.5 Data Setup, Hold and Slew Rate Derating
For all input signals the total t DS (setup time) and t DH (hold time) required is calculated by adding the
data sheet t DS(base) and t DH(base) value (see Table 54) to t he Δt DS and Δt DH (see Table 55 and Table
56) derating value respectively. Example: t DS (total setup time) = t DS(base) + Δt DS .
Setup (t DS ) nominal slew rate for a rising signal is defined as the slew rate between the last crossing
of V REF(DC) and the first crossing of V IH(AC) min. Setup (t DS ) nominal slew rate for a falling signal is
defined as the slew rate between the last crossing of V REF(DC) and the first crossing of V IL(AC) max
(see Figure 107). If the actual signal is always earlier than the nominal slew rate line between shaded
?V REF(DC) to AC region‘, use nominal slew rate for derating value. If the actual signal is later than the
nominal slew rate line anywhere between shaded ?V REF(DC) to AC region‘, the slew rate of a tangent
line to the actual signal from the AC level to V REF(DC) level is used for derating value (see Figure 109).
Hold (t DH ) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
V IL(DC) max and the first crossing of V REF(DC) . Hold (t DH ) nominal slew rate for a falling signal is
defined as the slew rate between the last crossing of V IH(DC) min and the first crossing of V REF(DC)
(see Figure 108). If the actual signal is always later than the nominal slew rate line between shaded
?DC level to V REF(DC) region‘, use nominal slew rate for derating value. If the actual signal is ear lier
than the nominal slew rate line anywhere between shaded ?DC to V REF(DC) region‘, the slew rat e of a
tangent line to the actual signal from the DC level to V REF(DC) level is used for derating value (see
Figure 110).
For a valid transition the input signal has to remain above/below V IH/IL(AC) for some time t VAC (see
Table 57).
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not
have reached V IH/IL(AC) at the time of the rising clock transition) a valid input signal is still required to
complete the transition and reach V IH/IL(AC) .
For slew rates in between the values listed in the tables the derating values may obtained by linear
interpolation.
These values are typically not subject to production test. They are verified by design and
characterization.
Table 54 – Data Setup and Hold Base-Values
Symbol
t DS(base) AC150
t DS(base) AC135
t DH(base) DC100
t DH(base) DC100
Reference
V IH/L(AC)
SR=1V/nS
V IH/L(AC)
SR=2V/nS
V IH/L(DC)
SR=1V/nS
V IH/L(DC)
SR=2V/nS
DDR3-1333
30
-
65
-
DDR3-1600
10
-
45
-
DDR3-1866
-
68
-
70
Unit
pS
pS
pS
pS
Notes
2
1
2
1
Notes:
1. (AC/DC referenced for 2V/nS DQ-slew rate and 4 V/nS DQS slew rate).
2. (AC/DC referenced for 1V/nS DQ-slew rate and 2 V/nS DQS slew rate).
Publication Release Date: Dec. 09, 2013
Revision A05
- 156 -
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