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| 型号： | W631GG6KB-15 |
| 厂商： | Winbond Electronics |
| 文件页数： | 96/159页 |
| 文件大小： | 0K |
| 描述： | IC DDR3 SDRAM 1GBIT 96WBGA |
| 标准包装： | 200 |
| 格式 - 存储器： | RAM |
| 存储器类型： | DDR3 SDRAM |
| 存储容量： | 1G（64M x 16） |
| 速度： | 667MHz |
| 接口： | 并联 |
| 电源电压： | 1.425 V ~ 1.575 V |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 96-TFBGA |
| 供应商设备封装： | 96-WBGA（9x13） |
| 包装： | 托盘 |
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W631GG6KB
9.2
CKE Truth Table
Notes 1-7 apply to the entire CKE Truth Table.
For Power-down entry and exit parameters See 8.17 “ Power-Down Modes ” on page 69.
CKE low is allowed only if t MRD and t MOD are satisfied.
Table 15 – CKE Truth Table
STATE
Current Cycle
COMMAND (N)
CURRENT
2
Previous Cycle
(N-1)
CKE
1
(N)
1
3
RAS#, CAS#, WE#, CS#
ACTION (N)
3
NOTES
Power Down
Self Refresh
Bank(s) Active
Reading
Writing
Precharging
Refreshing
All Banks Idle
L
L
L
L
H
H
H
H
H
H
H
L
H
L
H
L
L
L
L
L
L
L
X
DESELECT or NOP
X
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
REFRESH
Maintain Power Down
Power Down Exit
Maintain Self Refresh
Self Refresh Exit
Active Power Down Entry
Power Down Entry
Power Down Entry
Power Down Entry
Precharge Power Down Entry
Precharge Power Down Entry
Self Refresh
14,15
11,14
15,16
8,12,16
11,13,14
11,13,14,17
11,13,14,17
11,13,14,17
11
11,13,14,18
9,13,18
Any other state
Refer to section 9.1 “ Command Truth Table ” on Page 94 for more detail with all command signals
10
Notes:
1. CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge.
2. Current state is defined as the state of the DDR3 SDRAM immediately prior to clock edge N.
3. COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N), ODT is not
included here.
4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
6. During any CKE transition (registration of CKE H->L or CKE L->H) the CKE level must be maintained until 1nCK prior to
t CKE min being satisfied (at which time CKE may transition again).
7. DESELECT and NOP are defined in the Command Truth Table.
8. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the t XS period.
Read or ODT commands may be issued only after t XSDLL is satisfied.
9. Self Refresh mode can only be entered from the All Banks Idle state.
10. Must be a legal command as defined in the Command Truth Table.
11. Valid commands for Power Down Entry and Exit are NOP and DESELECT only.
12. Valid commands for Self Refresh Exit are NOP and DESELECT only.
13. Self Refresh can not be entered during Read or Write operations. For a detailed list of restrictions See section 8.16 “ Self-
Refresh Operation ” on page 67 and See section 8.17 “ Power-Down Modes ” on page 69.
14. The Power Down does not perform any refresh operations.
15. ―X‖ means ― don't care ‖ (including floating around V REF ) in Self Refresh and Power Down. It also applies to Address pins.
16. V REF (Both V REFDQ and V REFCA ) must be maintained during Self Refresh operation. V REFDQ supply may be turned OFF
and V REFDQ may take any value between V SS and V DD during Self Refresh operation, provided that V REFDQ is valid and
stable prior to CKE going back High and that first Write operation or first Write Leveling Activity may not occur earlier than
512 nCK after exit from Self Refresh.
17. If all banks are closed at the conclusion of the read, write or precharge command, then Precharge Power Down is entered,
otherwise Active Power Down is entered.
18. ?Idle state‘ is defined as all banks are closed (t RP , t DAL , etc. satisfied), no data bursts are in progress, CKE is high, and all
timings from previous operations are satisfied (t MRD , t MOD , t RFC , t ZQinit , t ZQ oper, t ZQCS , etc.) as well as all Self Refresh
exit and Power Down Exit parameters are satisfied (t XS , t XP , t XPDLL , etc).
Publication Release Date: Dec. 09, 2013
Revision A05
- 96 -
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