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| 型号： | W631GG6KB-15 |
| 厂商： | Winbond Electronics |
| 文件页数： | 80/159页 |
| 文件大小： | 0K |
| 描述： | IC DDR3 SDRAM 1GBIT 96WBGA |
| 标准包装： | 200 |
| 格式 - 存储器： | RAM |
| 存储器类型： | DDR3 SDRAM |
| 存储容量： | 1G（64M x 16） |
| 速度： | 667MHz |
| 接口： | 并联 |
| 电源电压： | 1.425 V ~ 1.575 V |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 96-TFBGA |
| 供应商设备封装： | 96-WBGA（9x13） |
| 包装： | 托盘 |
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W631GG6KB
8.19.2 Synchronous ODT Mode
Synchronous ODT mode is selected whenever the DLL is turned on and locked. Based on the power-
down definition, these modes are:
?
?
?
?
?
Any bank active with CKE high
Refresh with CKE high
Idle mode with CKE high
Active power down mode (regardless of MR0 bit A12)
Precharge power down mode if DLL is enabled during precharge power down by MR0 bit A12.
The direct ODT feature is not supported during DLL-off mode. The on-die termination resistors must
be disabled by continuously registering the ODT pin low and/or by programming the Rtt_Nom bits
MR1{A9,A6,A2} to {0,0,0} via a mode register set command during DLL-off mode.
In synchronous ODT mode, R TT will be turned on ODTLon clock cycles after ODT is sampled high by
a rising clock edge and turned off ODTLoff clock cycles after ODT is registered low by a rising clock
edge. The ODT latency is tied to the write latency (WL) by: ODTLon = WL - 2; ODTLoff = WL - 2.
8.19.2.1 ODT Latency and Posted ODT
In Synchronous ODT Mode, the Additive Latency (AL) programmed into the Mode Register (MR1) also
applies to the ODT signal. The DRAM internal ODT signal is delayed for a number of clock cycles
defined by the Additive Latency (AL) relative to the external ODT signal. ODTLon = CWL + AL - 2;
ODTLoff = CWL + AL - 2. For more details refer to the ODT timing parameters in section 10.16 “ AC
Characteristics ” on page 138.
Table 9 – ODT Latency
Symbol
ODTLon
ODTLoff
Parameter
ODT turn on Latency
ODT turn off Latency
DDR3-1333
DDR3-1600
WL - 2 = CWL + AL - 2
WL - 2 = CWL + AL - 2
DDR3-1866
Unit
n CK
8.19.2.2 Timing Parameters
In synchronous ODT mode, the following timing parameters apply (see also Figures 74):
ODTLon, ODTLoff, t AON ,min,max, t AOF ,min,max.
Minimum R TT turn-on time (t AON min) is the point in time when the device leaves high impedance and
ODT resistance begins to turn on. Maximum R TT turn on time (t AON max) is the point in time when the
ODT resistance is fully on. Both are measured from ODTLon.
Minimum R TT turn-off time (t AOF min) is the point in time when the device starts to turn off the ODT
resistance. Maximum R TT turn off time (t AOF max) is the point in time when the on-die termination has
reached high impedance. Both are measured from ODTLoff.
When ODT is asserted, it must remain high until ODTH4 is satisfied. If a Write command is registered
by the SDRAM with ODT high, then ODT must remain high until ODTH4 (BL = 4) or ODTH8 (BL = 8)
after the Write command (see Figure 75). ODTH4 and ODTH8 are measured from ODT registered
high to ODT registered low or from the registration of a Write command until ODT is registered low.
ODT must be held high for at least ODTH4 after assertion (T1); ODT must be kept high ODTH4 (BL =
4) or ODTH8 (BL = 8) after Write command (T7). ODTH is measured from ODT first registered high to
ODT first registered low, or from registration of Write command with ODT high to ODT registered low.
Note that although ODTH4 is satisfied from ODT registered high at T6, ODT must not go low before
T11 as ODTH4 must also be satisfied from the registration of the Write command at T7.
Publication Release Date: Dec. 09, 2013
Revision A05
- 80 -
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相关代理商/技术参数 |
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|---|---|
| W631GG8KB-11 | 制造商:Winbond Electronics Corp 功能描述:IC DDR3 SDRAM 1GBIT 制造商:Winbond Electronics Corp 功能描述:IC DDR3 SDRAM 1GBIT 78WBGA |
| W631GG8KB-12 | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR3 SDRAM 1G-Bit 128Mx8 1.5V 制造商:Winbond Electronics Corp 功能描述:IC DDR3 SDRAM 1GBIT 制造商:Winbond Electronics Corp 功能描述:IC DDR3 SDRAM 1GBIT 78WBGA |
| W631GG8KB-15 | 制造商:Winbond Electronics Corp 功能描述:IC DDR3 SDRAM 1GBIT 制造商:Winbond Electronics Corp 功能描述:IC DDR3 SDRAM 1GBIT 78WBGA |
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