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| 型号： | DS34S132GN+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 119/194页 |
| 文件大小： | 0K |
| 描述： | IC TDM OVER PACKET 676-BGA |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 40 |
| 功能： | TDM-over-Packet（TDMoP） |
| 接口： | TDMoP |
| 电路数： | 1 |
| 电源电压： | 1.8V, 3.3V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 676-BGA |
| 供应商设备封装： | 676-PBGA（27x27） |
| 包装： | 管件 |
| 其它名称： | 90-34S13+2N0 |
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DS34S132 DATA SHEET
19-4750; Rev1; 7/11
30 of 194
Each HDLC Bundle can be configured to support any number of DS0s up to the entire TDM Port line rate. In the
RXP direction the PW Header is stripped off and a Buffer is used to store the complete packet so that the packet’s
Ethernet FCS can be verified before transmitting the payload data at the TDM Port. In the TXP direction the HDLC
encoding is stripped off. When a complete HDLC frame has been received and the HDLC FCS has been verified,
the S132 appends a programmed TXP Bundle Header and generates a PW packet. A Timeslot Assignment block
provides a DS0 cross-connect function to interconnect the payload of any HDLC Bundle to any set of DS0 positions
on a single TDM Port.
9.1.3 SAT/CES PW-Timing Connections
SAT/CES TDMoP PW packets intrinsically always carry timing information by the constant periodic transmission
rate of the PW packets. The Adaptive Clock Recovery (ACR) technique takes advantage of this fact and does not
require that a TDMoP PW packet include a Timestamp header field. The Differential Clock Recovery (DCR)
Technique does not directly utilize the periodic transmission rate, but instead utilizes RTP Timestamps to indicate
the time differences between each successive PW packet. Every TDMoP PW packet includes ACR timing
information and can optionally include Timestamps.
When more than one TDMoP PWs are associated with a single TDM Port and the timing for that TDM Port uses
clock recovered timing, only one Bundle/PW can be programmed to include a PW-Timing Connection (to supply the
timing) and the frequency (data rate) for all of the other Bundle/PW streams assigned to that TDM Port must be
identical (synchronized). Otherwise the data, at the transmit TDM Port, for a non-synchronous PW would be
corrupted (the TDM Port can only transmit at one line rate). When timing information is included in PW packets, but
the Bundle does not include a PW-Timing Connection, the timing information is ignored by the S132.
The DS34S132 internal PW-Timing Connections are used by the RXP Clock Recovery Engines and the TXP RTP
Timestamp Generator. PW-Timing Connections can be set up in either direction or in both directions. The RXP and
TXP PW-Timing Connections are diagramed in Figure 9-5.
Figure 9-5. Bundle PW-Timing Connections
DS34S132
TXP SAT/CES Engine Timing
RTP Timestamp Generator
TXP Pkt
Generator
Rcv TDM Timing
TXP Timing
RXP SAT/CES Engine Timing
Clock Recovery Engine
TDM
Port
RXP Pkt
Classifier
Ethernet
MAC
Xmt TDM Timing
RXP Timing
The S132 supports up to 32 RXP Clock Recovery PW-Timing Connections (one for each transmit TDM Port) and
up to 256 TXP, RTP Timestamp, PW-Timing Connections (one for each TXP Bundle). Each RXP PW-Timing
Connection is programmed as part of the RXP Bundle parameters. Each TXP PW-Timing Connection is enabled by
programming the TXP Header Descriptor to include an RTP Header.
In the RXP direction the Classifier identifies the packets for an RXP PW-Timing Connection when a received packet
matches the Header protocol and BID of a Bundle and that Bundle is programmed for “Clock Recovery”. The PW-
Timing information from the packet is forwarded to the appropriate Clock Recovery Engine which in turn is used to
drive the timing of a transmit TDM Port. The clock recovery timing information can be derived from the RXP packet
rate (ACR) or RTP Differential Timestamps (DCR-DT).
In the TXP direction, the PW timing information is derived from the receive TDM Port. A TXP packet is periodically
generated when the prescribed amount of SAT/CES Payload has been received from the TDM Port. The TXP PW-
Timing information is conveyed through the rate at which TXP packets are transmitted (ACR) but can also be
supplemented by inserting an optional TXP RTP Timestamp. The TXP PW-Timing Connection (when
included/enabled in a TXP Bundle) inserts the optional TXP RTP Timestamp. The TXP PW-Timing Connection is
not required if the far end clock recovery uses the ACR technique.
A Bundle that includes a PW-Timing Connection (RXP and/or TXP direction) can also include a SAT/CES Payload
Connection. If the Bundle does not include a SAT/CES Connection, the Bundle/PW is called a “Clock Only”
Bundle/PW. Clock Only packets do not include payload data, but instead only carry the timing information
(conveyed through the packet transmission rate and/or RTP Timestamps).
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| DS34S132GN+ | 功能描述:通信集成电路 - 若干 32Port TDM-Over-Pack Transport Device RoHS:否 制造商:Maxim Integrated 类型:Transport Devices 封装 / 箱体:TECSBGA-256 数据速率:100 Mbps 电源电压-最大:1.89 V, 3.465 V 电源电压-最小:1.71 V, 3.135 V 电源电流:50 mA, 225 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装:Tube |
| DS34S132GNA2+ | 功能描述:通信集成电路 - 若干 32Port TDM-Over-Pack Transport Device RoHS:否 制造商:Maxim Integrated 类型:Transport Devices 封装 / 箱体:TECSBGA-256 数据速率:100 Mbps 电源电压-最大:1.89 V, 3.465 V 电源电压-最小:1.71 V, 3.135 V 电源电流:50 mA, 225 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装:Tube |
| DS34T101 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
| DS34T101_08 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
| DS34T101_09 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
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