
DS34S132 DATA SHEET
19-4750; Rev 1; 07/11
109 of 194
JB. Field
Name
Addr (A:)
Bit [x:y] Type
Description
G21SRIE. A:02D4h
Group 21 Status Register Interrupt Enable. Default: 0x00.00.00.00
RSVD
[31:8]
Reserved.
JBUIE
[175:168]
[7:0] rwc-_-i3
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JB.G21SRL[z] = 1 and JB.G21SRIE[z] = 1, forces G.GSR6[21] = 1.
G22SRIE. A:02D8h
Group 22 Status Register Interrupt Enable. Default: 0x00.00.00.00
RSVD
[31:8]
Reserved.
JBUIE
[183:176]
[7:0] rwc-_-i3
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JB.G22SRL[z] = 1 and JB.G22SRIE[z] = 1, forces G.GSR6[22] = 1.
G23SRIE. A:02DCh
Group 23 Status Register Interrupt Enable. Default: 0x00.00.00.00
RSVD
[31:8]
Reserved.
JBUIE
[191:184]
[7:0] rwc-_-i3
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JB.G23SRL[z] = 1 and JB.G23SRIE[z] = 1, forces G.GSR6[23] = 1.
G24SRIE. A:02E0h
Group 24 Status Register Interrupt Enable. Default: 0x00.00.00.00
RSVD
[31:8]
Reserved.
JBUIE
[199:192]
[7:0] rwc-_-i3
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JB.G24SRL[z] = 1 and JB.G24SRIE[z] = 1, forces G.GSR6[24] = 1.
G25SRIE. A:02E4h
Group 25 Status Register Interrupt Enable. Default: 0x00.00.00.00
RSVD
[31:8]
Reserved.
JBUIE
[207:200]
[7:0] rwc-_-i3
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JB.G25SRL[z] = 1 and JB.G25SRIE[z] = 1, forces G.GSR6[25] = 1.
G26SRIE. A:02E8h
Group 26 Status Register Interrupt Enable. Default: 0x00.00.00.00
RSVD
[31:8]
Reserved.
JBUIE
[215:208]
[7:0] rwc-_-i3
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JB.G26SRL[z] = 1 and JB.G26SRIE[z] = 1, forces G.GSR6[26] = 1.
G27SRIE. A:02ECh
Group 27 Status Register Interrupt Enable. Default: 0x00.00.00.00
RSVD
[31:8]
Reserved.
JBUIE
[223:216]
[7:0] rwc-_-i3
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JB.G27SRL[z] = 1 and JB.G27SRIE[z] = 1, forces G.GSR6[27] = 1.
G28SRIE. A:02F0h
Group 28 Status Register Interrupt Enable. Default: 0x00.00.00.00
RSVD
[31:8]
Reserved.
JBUIE
[231:224]
[7:0] rwc-_-i3
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JB.G28SRL[z] = 1 and JB.G28SRIE[z] = 1, forces G.GSR6[28] = 1.
G29SRIE. A:02F4h
Group 29 Status Register Interrupt Enable. Default: 0x00.00.00.00
RSVD
[31:8]
Reserved.
JBUIE
[239:232]
[7:0] rwc-_-i3
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JB.G29SRL[z] = 1 and JB.G29SRIE[z] = 1, forces G.GSR6[29] = 1.
G30SRIE. A:02F8h
Group 30 Status Register Interrupt Enable. Default: 0x00.00.00.00
RSVD
[31:8]
Reserved.
JBUIE
[247:240]
[7:0] rwc-_-i3
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JB.G30SRL[z] = 1 and JB.G30SRIE[z] = 1, forces G.GSR6[30] = 1.
G31SRIE. A:02FCh
Group 31 Status Register Interrupt Enable. Default: 0x00.00.00.00
RSVD
[31:8]
Reserved.
JBUIE
[255:248]
[7:0] rwc-_-i3
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JB.G31SRL[z] = 1 and JB.G31SRIE[z] = 1, forces G.GSR6[31] = 1.