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参数资料
| 型号： | DS34S132GN+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 141/194页 |
| 文件大小： | 0K |
| 描述： | IC TDM OVER PACKET 676-BGA |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 40 |
| 功能： | TDM-over-Packet（TDMoP） |
| 接口： | TDMoP |
| 电路数： | 1 |
| 电源电压： | 1.8V, 3.3V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 676-BGA |
| 供应商设备封装： | 676-PBGA（27x27） |
| 包装： | 管件 |
| 其它名称： | 90-34S13+2N0 |
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DS34S132 DATA SHEET
19-4750; Rev 1; 07/11
50 of 194
The Jitter Buffer Maximum Fill Level generally determines the maximum delay. Although the fill level will initially
stabilize at a level just high enough to support the Total PDV, when anomalies occur (e.g. temporary line failures
and RXP PW protection switching) the Jitter Buffer can fill beyond the “Total PDV” level. If the Jitter Buffer fill level
is not “corrected” after an anomaly, because of the near constant rate of the transmit TDM Port, the “extra” data will
not dissipate and will increase the total delay. For example if the Maximum Fill Level is programmed to 1 second
(MJBS or JBMD), and the Total PDV is 10 ms, initially the Jitter Buffer may stabilize at a 10 ms level. But anomalies
could cause the Jitter Buffer to fill beyond the 10 ms level (e.g. equipment programming changes) and as more
anomalies occur, the fill level could accumulate to any level up to 1 second.
There are several registers that the CPU can use to monitor the Jitter Buffer Fill level. Monitoring can be
implemented by polling the Jitter Buffer Maximum and Minimum fill levels or by monitoring for Overrun/Underrun
event indications (data discarded or dummy data inserted). The Jitter Buffer Fill Levels can help to identify setup
errors. Other Jitter Buffer functions that can be enabled include Packet Reordering (for packets received out of
order), packet discard monitoring for too early, too late and duplicate packet Sequence Number. The registers that
support these Jitter Buffer functions include: G.GCR.IPSE, G.GCR.RDPC, G.GSR1.JBS, G.GSRIE1.JBUIE,
G.GSR6.JBGS, PC.CR1.DPDE, B.BCDR1.SCSNRE, B.BDSRL1.JBLPDSL, B.BDSR2 - B.BDSR3, B.BDSR5 -
B.BDSR7, B.GxSRL, and JB.GxSRL.
A Jitter Buffer overflow can occur for three reasons: the selected Transmit TDM Port clock is not the same rate as
that used by the RXP packets (i.e. the wrong clock was selected); clock recovery is selected but has not yet fully
converged to the RXP Packet data rate and is running too slow; the Jitter Buffer depth is too small to handle the
maximum incoming PDV.
The Jitter Buffer is also used by HDLC Connections. However, HDLC Connections, in general, do not transport
constant bit rate data streams (unlike SAT/CES Payload Connections), so the Jitter Buffer is instead used as a
more simplistic FIFO. The Jitter Buffer PDVT and MJBS settings, and the Packet Reordering, Early/Late and
Duplicate Discard functions do not have any meaning with HDLC Connections. HDLC data is forwarded as soon as
it is available. JBMD defines the depth of the FIFO.
9.2.6 TDM Diagnostic Functions
The S132 supports TDM Loopback and TDM BERT Functions for diagnostic testing of the TDM Ports.
9.2.6.1 TDM Loopback
The S132 supports 3 types of Loopbacks for the TDM Ports: TDM Port Line Loopback, TDM Port Timeslot
Loopback and Bundle Loopback. Any number of TDM Ports can be in loopback at the same time.
The TDM Port Line Loopback is enabled using Pn.PTCR2.PRPTLL. This loopback takes data from RDAT and re-
transmits that data on TDAT. All data that is received on RDAT is looped back to TDAT.
The TDM Port Timeslot Loopback is enabled using Pn.PTCR3.PRPTTSL (32 bits, one for each TDM Port
Timeslot). This loopback also takes data from RDAT and re-transmits that data on TDAT, but only for those
Timeslots that have the loopback function enabled. Timeslots that do not have the loopback function enabled
continue to pass data (from Receive TDM Port to TXP Packet and from RXP packet to transmit TDM Port).
For either of these loopbacks to function properly the programmed Transmit TDM Port clock and synchronization
sources (when applicable) must be set to be the same as that of the Receive TDM Port.
When either loopback is enabled, the data for receive TDM Timeslots, that are in loopback, will continue to be
transmitted in TXP packets if TXP Bundles are assigned to the Receive TDM Port and enabled. The TXP packet
stream can be disabled by de-activating the Bundle or by disabling TXP Bundle transmission (B.BCDR3.TXPMS).
RXP Packet data that is received for Timeslots that are in loopback is still forwarded to the Jitter Buffer and is still
used for Clock Recovery. When the loopback is removed, any data that is waiting in the Jitter Buffer is forwarded to
the TDM Port. To prevent the Jitter Buffer from filling with data during a loopback, the payload data for a Bundle
can be discarded (B.BCDR4.RXBDS). Clock Recovery will continue to function for an RXP Bundle that is in one of
these 2 loopbacks as long as the Bundle is selected for Clock Recovery (B.BCDR4.PCRE).
The Transmit TDM Port can only use one timing source, so caution must be exercised when enabling loopbacks for
some Timeslots while other Timeslots are not in loopback. A frequency difference between the looped back RDAT
data and the (non-looped) RXP Packet data will result in occasional slips (corrupted data).
These 2 loopbacks are depicted in Figure 9-17 using a T1/E1 example. The arrow depicts the loopback direction.
The diagram does not depict how “normal” data continues to be forwarded to/from the Ethernet Phy.
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相关代理商/技术参数 |
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| DS34S132GN+ | 功能描述:通信集成电路 - 若干 32Port TDM-Over-Pack Transport Device RoHS:否 制造商:Maxim Integrated 类型:Transport Devices 封装 / 箱体:TECSBGA-256 数据速率:100 Mbps 电源电压-最大:1.89 V, 3.465 V 电源电压-最小:1.71 V, 3.135 V 电源电流:50 mA, 225 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装:Tube |
| DS34S132GNA2+ | 功能描述:通信集成电路 - 若干 32Port TDM-Over-Pack Transport Device RoHS:否 制造商:Maxim Integrated 类型:Transport Devices 封装 / 箱体:TECSBGA-256 数据速率:100 Mbps 电源电压-最大:1.89 V, 3.465 V 电源电压-最小:1.71 V, 3.135 V 电源电流:50 mA, 225 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装:Tube |
| DS34T101 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
| DS34T101_08 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
| DS34T101_09 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
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