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| 型号： | DS34S132GN+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 155/194页 |
| 文件大小： | 0K |
| 描述： | IC TDM OVER PACKET 676-BGA |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 40 |
| 功能： | TDM-over-Packet（TDMoP） |
| 接口： | TDMoP |
| 电路数： | 1 |
| 电源电压： | 1.8V, 3.3V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 676-BGA |
| 供应商设备封装： | 676-PBGA（27x27） |
| 包装： | 管件 |
| 其它名称： | 90-34S13+2N0 |
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DS34S132 DATA SHEET
19-4750; Rev 1; 07/11
63 of 194
TXP SAT/CES/Clock Only Packets can optionally include an RTP Timestamp using the RTP Exists field in the TXP
Header Descriptor Header Control (RTP is not commonly used with HDLC Bundles).
A TXP HDLC packet is generated for each HDLC packet that is received from the TDM Port with a correct HDLC
FCS value. The HDLC packet encoding is removed before the TXP Header is appended. HDLC packets that are
received with bad HDLC FCS values are discarded. HDLC TXP Packet transmission can be enable/disabled using
B.BCDR3.TXPMS.
The IP Length, IP FCS, UDP Length and UDP FCS fields are auto generated for SAT, CES, HDLC and Clock Only
packets when these fields are enabled by the TXP Header Descriptor Header Control.
9.3.3.1.1 L-bit Signaling
The L-bit in the Control Word of a PW packet can be used to indicate, across the PSN, when the data contained in
a TDMoP PW payload may be corrupted (e.g. for a T1/E1 LOS condition, L-bit = 1). The Pn.PRCR1.LBSS register
selects whether the L-bit in each TXP Packet is controlled on a “per-Bundle basis” using the TXP Header
Descriptor or on a “per-TDM Port basis” using Pn.PRCR1.LB. When the “per-Bundle” method is selected, the CPU
must modify all of the programmed TXP Header Descriptors that are associated with a TDM Port that requires an L-
bit change. When the “per-TDM Port” method is selected, changing Pn.PRCR1.LB changes the L-bit value in all
TXP Packets for that TDM Port.
The standards allow TXP SAT/CES PW packets, to optionally truncate/remove the payload section when the TXP
L-bit = 1 to save network bandwidth during receive TDM fault conditions (detected by the external TDM Port
Framer/LIU). B.BCDR3.TXPMS can be programmed to “transmit without payload”, so that the TXP Bundle packet
transmit rate does not change but with a smaller packet size (like that of a Clock Only packet).
9.3.3.2 TXP CPU Packet Generation
The generation of TXP Bundle packets is described in the “TXP CPU Packet Interface” section.
9.3.3.3 TXP Packet Scheduling
The transmit PDV for Bundles that are used for clock recovery can be minimized to improve the clock recovery
performance at the far end by programming the TXP Bundle with the high scheduling priority (B.BCDR3.TXBPS)
and, for networks that support VLAN CoS, by assigning a high P-bit priority in the VLAN tag (the P-bit value is
provided by the CPU in the TXP Header Descriptor; high priority packets are processed before low priority
packets). Bundles that can be used for Clock Recovery include SAT/CES Bundles with payload and Clock Only
Bundles without payload. The TXP Clock Only Bundle is designed to provide the best possible transmit PDV and
latency by suppressing the payload. HDLC Bundles should normally be assigned low priority (B.BCDR3.TXBPS).
9.3.3.4 TXP Packet Queue Monitoring
The TXP Packet Queue fill levels can be monitored using the G.TPISR1 (TXP Bundle High Priority Queue),
G.TPISR2 (TXP Bundle Low Priority Queue) and G.TPISR3 (TXP CPU Queue) registers. Each of these queues
also provides a maskable interrupt using G.TPISRL.HPQOSL, G.TPISRL.LPQOSL and EMA.WSRL1.WFOSL.
9.4 CPU Packet Interface
Up to 512 stored RXP CPU packets
RXP CPU packet size up to 2000 bytes
RXP Local Timestamp
RXP Packet Classification Results
Up to 512 stored TXP CPU packets
TXP CPU packet size up to 2000 bytes
TXP RTP (OAM) Timestamp generation
RXP CPU Packets that are received from the Ethernet Port are stored in an SDRAM RXP CPU Queue for the CPU
to Read. The CPU Writes TXP CPU Packets into an SDRAM TXP CPU Queue that are later transmitted at the
Ethernet Port. The depth of the RXP CPU FIFO and TXP CPU Queues are programmed at EMI.BMCR3.PRSO and
EMI.BMCR3.PRSO.
9.4.1 RXP CPU Packet Interface
RXP CPU Packets that are received at the Ethernet Port are stored in 2 Kbyte slots in the SDRAM RXP CPU
Queue. The S132 stores an RXP CPU Header Descriptor with each RXP CPU packet to provide information about
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| DS34S132GN+ | 功能描述:通信集成电路 - 若干 32Port TDM-Over-Pack Transport Device RoHS:否 制造商:Maxim Integrated 类型:Transport Devices 封装 / 箱体:TECSBGA-256 数据速率:100 Mbps 电源电压-最大:1.89 V, 3.465 V 电源电压-最小:1.71 V, 3.135 V 电源电流:50 mA, 225 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装:Tube |
| DS34S132GNA2+ | 功能描述:通信集成电路 - 若干 32Port TDM-Over-Pack Transport Device RoHS:否 制造商:Maxim Integrated 类型:Transport Devices 封装 / 箱体:TECSBGA-256 数据速率:100 Mbps 电源电压-最大:1.89 V, 3.465 V 电源电压-最小:1.71 V, 3.135 V 电源电流:50 mA, 225 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装:Tube |
| DS34T101 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
| DS34T101_08 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
| DS34T101_09 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
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