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参数资料
| 型号： | DS34S132GN+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 136/194页 |
| 文件大小： | 0K |
| 描述： | IC TDM OVER PACKET 676-BGA |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 40 |
| 功能： | TDM-over-Packet（TDMoP） |
| 接口： | TDMoP |
| 电路数： | 1 |
| 电源电压： | 1.8V, 3.3V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 676-BGA |
| 供应商设备封装： | 676-PBGA（27x27） |
| 包装： | 管件 |
| 其它名称： | 90-34S13+2N0 |
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DS34S132 DATA SHEET
19-4750; Rev 1; 07/11
46 of 194
The delay of data at the input of the Jitter Buffer is caused by fixed and PDV (variable) delay parameters according
to the equation below.
Maximum Jitter Buffer Input Delay = PCT + fixed transmission and circuit processing delay + Total PDV
PCT (Packet Creation Time) is a fixed delay that is equal to the amount of time that it takes to receive enough data
from a TDM Port to fill the Payload section of a PW Bundle. The B.BCDR1.PMS (Packet Payload Size) setting is
programmed according to the desired PCT value using the equations below. For example it may be desirable for a
CES payload to carry 8 frames of data (from the equations below, PCT = 1 ms and PMS = 8).
T1/E1 Nx64 CES: B.BCDR1.PMS = “# T1/E1 Frames per Packet Payload” = PCT ÷ 125us
T1 SAT:
B.BCDR1.PMS = “# bytes per Packet Payload” = PCT ÷ 5.2us
E1 SAT:
B.BCDR1.PMS = “# bytes per Packet Payload” = PCT ÷ 3.9us
“Slow rate” SAT:
B.BCDR1.PMS = “# bytes per Packet Payload” = PCT ÷ (8/fTDM)
(where “fTDM” is equal to the data bit rate at the TDM Port).
The fixed transmission delay will differ for each PW connection according to the distance between the end points
(e.g. a signal may take 500 us to travel 100 km). The fixed circuit processing delay varies according to the type and
number of network nodes (e.g. routers) and the S132 fixed circuit delays. These fixed delays do not affect the Clock
Recovery performance or Jitter Buffer depth (unless they change, e.g. when switching to a backup/protection line).
PDV is caused when congestion occurs at a port that has more than one packet waiting to be transmitted and can
be caused by circuits that process data in “blocks” (delayed waiting to finish a block).
There are several PDV parameters that are identified in the equation below and described in Table 9-6.
Total PDV = Network PDV + S132 Ether Media PDV + S132 Schedule PDV + S132 BFD PDV + S132 MTIE PDV
Table 9-6. PDV Parameters that affect the latency of a PW packet
PDV Type
Description
Network
PDV:
Network PDV is generated by the packet switches between the two PW End Points. Each packet
switch becomes congested when more than one incoming switch port has a packet to send to the
same outgoing switch Port (one incoming packet must wait for the other). For example some
networks may assume that each packet switch might introduce up to 1 ms of PDV.
S132
Ethernet
Media
PDV:
S132 Ethernet Media PDV is generated when the Ethernet Port Line Rate (100 Mb/s or 1000 Mb/s)
delays the delivery of the packet because the line rate is unable to transmit infinitely fast. For
example if 32 packets that are 64 bytes in length, are waiting to be transmitted at the S132 Ethernet
Port, the last packet will not be transmitted until after the 31 other packets are transmitted. The
Ethernet Media PDV can be a large number. For this reason, the 1000 Mb/s line rate should be used
whenever possible to minimize this parameter. The Ethernet Media PDV is dependent on the
Ethernet line rate, the number of Bundles, the size of the Ethernet packets that are being transmitted
and includes the Ethernet 20-byte Inter-packet Gap (IPG). The equation below assumes all of the
Bundles use the same packet size. Table 9-7 provides 6 examples that use this equation.
S132 Ethernet Media PDV = [# Bundles * (# pkt bytes + 20 byte IPG) * 8 bits/byte] ÷ line rate
S132 RXP
& TXP
Scheduling
PDV:
The S132 RXP and TXP Scheduling PDV values are caused by the limited rate at which data can be
transferred to/from the SDRAM. Similar to the Ethernet Media PDV, if 32 packets are ready (in the
SDRAM) to be sent, the S132 Buffer Manager can only retrieve one packet at a time and the last
packet is delayed waiting for the other 31 packets. This PDV parameter increases the Total PDV only
if the Ethernet Media is able to forward packets faster than the S132 Buffer Manager can retrieve the
packets from the SDRAM (i.e. the Scheduling PDV is “hidden” by the Ethernet Media PDV as long as
the Buffer Manager can keep up with the Ethernet Port transmission rate).
S132 RXP
& TXP BFD
PDV:
The S132 RXP and TXP BFD PDV values are caused as the S132 waits for sufficient data to fill the
SDRAM Staging Buffers. The depths of these buffers are programmed using the BFD registers to
determine the data block size that is used to store and retrieve data from the SDRAM. This PDV
parameter can vary from 125 us to 500 us according to the BFD setting (one in each direction).
S132 RXP
MTIE PDV:
The S132 MTIE PDV is generated by the varying output frequency of the Clock Recovery Engine.
Before the Clock Recovery Engine has locked to the incoming RXP packet rate, the transmit TDM
Port line rate can vary (slightly) adding to the Total PDV. After the Clock Recovery Engine is locked
to the RXP data rate, this parameter becomes insignificant. This parameter is difficult to characterize,
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| DS34S132GN+ | 功能描述:通信集成电路 - 若干 32Port TDM-Over-Pack Transport Device RoHS:否 制造商:Maxim Integrated 类型:Transport Devices 封装 / 箱体:TECSBGA-256 数据速率:100 Mbps 电源电压-最大:1.89 V, 3.465 V 电源电压-最小:1.71 V, 3.135 V 电源电流:50 mA, 225 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装:Tube |
| DS34S132GNA2+ | 功能描述:通信集成电路 - 若干 32Port TDM-Over-Pack Transport Device RoHS:否 制造商:Maxim Integrated 类型:Transport Devices 封装 / 箱体:TECSBGA-256 数据速率:100 Mbps 电源电压-最大:1.89 V, 3.465 V 电源电压-最小:1.71 V, 3.135 V 电源电流:50 mA, 225 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装:Tube |
| DS34T101 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
| DS34T101_08 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
| DS34T101_09 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
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