- 您现在的位置：买卖IC网 > PDF目录1916 > DS34S132GN+ (Maxim Integrated Products)IC TDM OVER PACKET 676-BGA PDF资料下载
参数资料
| 型号： | DS34S132GN+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 133/194页 |
| 文件大小： | 0K |
| 描述： | IC TDM OVER PACKET 676-BGA |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 40 |
| 功能： | TDM-over-Packet（TDMoP） |
| 接口： | TDMoP |
| 电路数： | 1 |
| 电源电压： | 1.8V, 3.3V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 676-BGA |
| 供应商设备封装： | 676-PBGA（27x27） |
| 包装： | 管件 |
| 其它名称： | 90-34S13+2N0 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页当前第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页第165页第166页第167页第168页第169页第170页第171页第172页第173页第174页第175页第176页第177页第178页第179页第180页第181页第182页第183页第184页第185页第186页第187页第188页第189页第190页第191页第192页第193页第194页
DS34S132 DATA SHEET
19-4750; Rev 1; 07/11
43 of 194
a Bundle is equivalent to enabling a “Connection” for that Engine (e.g. enabling SAT/CES Engine = enable
SAT/CES Connection). B.BCDR1.RXBDS further supplements these selections by providing the ability to instead
forward the packets for a Bundle to the CPU (for debug; CPU Debug RXP PW Bundle) or to discard the packet
payload for Clock Only Bundles (to reduce the S132 payload processing functions). The following types of Bundles
can be programmed using these registers. The “Register Definition” and the “Register Guide” sections provide
more information on how to set these registers for each Bundle type.
SAT
Nx64 CES without CAS
Nx64 CES with CAS
HDLC for Unstructured TDM Port
Structured Nx64 HDLC
Structured 56 Kb/s or 16 Kb/s HDLC
SAT Clock Only
CES Clock Only
The SAT and CES Bundles can include an RXP PW-Timing Connection by enabling B.BCDR4.PCRE and/or a TXP
PW-Timing Connection by including the RTP Timestamp in the TXP Header Descriptor for that Bundle (see the
“TXP SAT/CES and HDLC PW Packet Generation” section). The Clock Recovery functions are described in more
detail in the “PW-Timing” section.
All of the Bundle types can include support for In-band VCCV (In-band VCCV CPU Connection). When a packet is
received for a recognized Bundle, the received packet header matches the In-band VCCV Control Word
(PC.CR5.VOV and PC.CR5.VOM) and In-band VCCV has been enabled for that Bundle (B.BCDR4.RXCWE and
B.BCDR4.RXOICWE) the S132 forwards the In-band VCCV packet to the CPU or discards the packet according to
the PC.CR1.DPS7 setting (OAM Packet Discard switch; this switch also affects other OAM types).
In the TXP direction, Receive TDM Port data that is ready for transmission is buffered in one of two priority queues
so that the packets can be scheduled according to their importance when congestion occurs. TXP Packets that are
buffered in the higher priority queue are processed before TXP Packets in the lower priority queue. For example,
Bundles with PW-Timing Connections can be assigned to the higher priority queue. The TXP priority is selected for
each TXP Bundle using B.BCDR3.TXBPS.
9.2.5.1 HDLC Engine
The S132 includes 256 HDLC Engines, one each for up to 256 Bundles. Several HDLC Bundle types are supported
including Unstructured HDLC (full TDM Port bandwidth), Structured Nx64 Kb/s HDLC, Structured 56 Kb/s or
Structured 16 Kb/s. With HDLC Bundles the terms “Unstructured” and “Structured” refer to the format of the TDM
Port. These terms do not have any direct relevance to the packet format of an HDLC Bundle. A single Structured
TDM Port can support any combination of Structured HDLC Bundles and CES Bundles since each Bundle can be
assigned to independent Timeslots on a Structured TDM Port.
Figure 9-14. HDLC Engine Environment
DS34S132
TXP
TSA
RXP
TSA
TXP HDLC Engine
RXP HDLC Engine
Buffer
Manager
HDLC
Connection
An Unstructured HDLC Bundle uses the entire bandwidth of its assigned TDM Port. The HDLC coding/decoding is
performed using the entire data stream without regard for T1/E1 framing or Timeslot positions.
Structured HDLC Bundles can be programmed to use 2-bit, 7-bit or 8-bit HDLC coding (for 16 Kb/s, 56 Kb/s and
“Nx64 Kb/s” channels respectively; B.BCDR1.SCTXCOS). The bit-width setting identifies how many bits are used in
the assigned Timeslot. For 8-bit, all 8 bits of the timeslot are HDLC coded. For 7-bit coding, only the 7 MSbits are
HDLC coded (the LSbit is unused). For 2-bit coding, the two MSbits or two LSbits can be selected for HDLC coding
(the remaining 6-bits are unused). Unstructured HDLC Bundles always use 8-bit coding.
The “8-bit” format allows an HDLC Bundle to combine the data from multiple 8-bit Timeslots of a single Structured
T1/E1 to support bandwidths like 384 Kb/s (using six 8-bit Timeslots). Any number of 8-bit Timeslots can be
combined (up to 24 for Structured T1 or 31 for Structured E1).
Only one 2-bit or 7-bit HDLC coded Timeslot from a Structured T1/E1 can be assigned to an HDLC Bundle.
相关PDF资料 |
PDF描述 |
|---|---|
| DS34T102GN+ | IC TDM OVER PACKET 484TEBGA |
| DS3501U+H | IC POT NV 128POS HV 10-USOP |
| DS3502U+ | IC POT DGTL NV 128TAP 10-MSOP |
| DS3503U+ | IC POT DGTL NV 128TAP 10-MSOP |
| DS3897MX | IC TXRX BTL TRAPEZIODAL 20-SOIC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS34S132GN+ | 功能描述:通信集成电路 - 若干 32Port TDM-Over-Pack Transport Device RoHS:否 制造商:Maxim Integrated 类型:Transport Devices 封装 / 箱体:TECSBGA-256 数据速率:100 Mbps 电源电压-最大:1.89 V, 3.465 V 电源电压-最小:1.71 V, 3.135 V 电源电流:50 mA, 225 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装:Tube |
| DS34S132GNA2+ | 功能描述:通信集成电路 - 若干 32Port TDM-Over-Pack Transport Device RoHS:否 制造商:Maxim Integrated 类型:Transport Devices 封装 / 箱体:TECSBGA-256 数据速率:100 Mbps 电源电压-最大:1.89 V, 3.465 V 电源电压-最小:1.71 V, 3.135 V 电源电流:50 mA, 225 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装:Tube |
| DS34T101 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
| DS34T101_08 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
| DS34T101_09 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
发布紧急采购，3分钟左右您将得到回复。