
DS34S132 DATA SHEET
19-4750; Rev 1; 07/11
113 of 194
PC. Field
Name
Addr (A:)
Bit [x:y] Type
Description
CR14.
A:0334h
Configuration Register 14. Default: 0x00.00.00.00
IV6A2B
[31:0] rwc-_-_
IPv6 Address 2 B-bits programs bits 32 to 63 of the 2nd 128-bit IPv6 Destination
Address.
CR15.
A:0338h
Configuration Register 15. Default: 0x00.00.00.00
IV6A2C
[31:0] rwc-_-_
IPv6 Address 2 C-bits programs bits 64 to 95 of the 2nd 128-bit IPv6 Destination
Address.
CR16.
A:033Ch
Configuration Register 16. Default: 0x00.00.00.00
IV6A2D
[31:0] rwc-_-_
IPv6 Address 2 D-bits programs bits 96 to 127 of the 2nd 128-bit IPv6 Destination
Address.
CR17.
A:0340h
Configuration Register 17. Default: 0x00.00.00.00
MA1B
[31:0] rwc-_-_
MAC Address 1 B-bits programs bits 16 to 47 of the 1st 48-bit Ethernet
Destination Address.
CR18.
A:0344h
Configuration Register 18. Default: 0x00.00.00.00
MA1A
[31:16] rwc-_-_
MAC Address 1 A-bits programs bits 0 to 15 of the 1st 48-bit Ethernet
Destination Address.
MA2A
[15:0] rwc-_-_
MAC Address 2 A-bits programs bits 0 to 15 of the 2nd 48-bit Ethernet
Destination Address.
CR19.
A:0348h
Configuration Register 19. Default: 0x00.00.00.00
MA2B
[31:0] rwc-_-_
MAC Address 2 B-bits programs bits 16 to 47 of the 2nd 48-bit Ethernet
Destination Address.
CR20.
A:034Ch
Configuration Register 20. Default: 0x00.00.00.00
CDET
[31:16] rwc-_-_
CPU Destination Ether Type programs the Ethernet Type field value that is used
to identify “CPU Destination Ethernet Type” packets.
UBIDM
[15:0] rwc-_-_
UDP Bundle ID Mask selects which of the 16 LSB of a received UDP BID or
OAM BID are tested for a match (“1” = test for match; “0” = ignore bit). For 32-bit
UDP BIDs and 0AM BIDs the 16 MSB are always tested.
CR21.
A:0350h
Configuration Register 21. Default: 0x00.00.00.03
RSVD
[31:8]
Reserved.
PDCC
[7:4] rwc-_-_
Packet stream Defect Count Control selects which Jitter Buffer fill defect
conditions are counted by G.BDSR1.PDC (one bit per defect function; 1 = enable;
any combination can be enabled): Too Early (bit 7), Too Late (bit 6), Overrun (bit
5), Underrun (bit 4). The Overrun level is programmed using B.BCDR5.MJBS.
JBECC
[3:0] rwc-_-_
Jitter Buffer Event Count Control selects which Jitter Buffer fill defect conditions
are counted by G.BDSR2.JBEC (one bit per defect function; 1 = enable; any
combination can be enabled): Too Early (bit 7), Too Late (bit 6), Overrun (bit 5),
Underrun (bit 4). The Overrun level is programmed using B.BCDR5.MJBS.
10.3.4.2 Packet Classifier Status Register Latches (PC.)
Table 10-14. Packet Classifier Register Latches (PC.)
PC. Field
Name
Addr (A:)
Bit [x:y] Type
Description
SRL.
A:0360h
Status Register Latch. Default: 0x00.00.00.00
RSVD
[31:8]
Reserved.
VMDSL
[7] rls-crw-i3
VLAN Mismatch Discard Status Latch = “1” indicates 1 or more RXP packets
have been received with an Outer VLAN TPID that matched PC.CR3.VOTPID, but
the Inner VLAN TPID did not match PC.CR3.VITPID.