参数资料
| 型号： | IP-SDI |
| 厂商： | Altera |
| 文件页数： | 104/140页 |
| 文件大小： | 0K |
| 描述： | IP VIDEO INTERFACE - SDI |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | 视频系统用串行数字接口 |
| 许可证： | 初始许可证 |
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4–16
Chapter 4: SDI Audio IP Cores
SDI Audio Extract MegaCore Function
Table 4–17. SDI Audio Extract MegaCore Function Register Map (Part 2 of 2)
Bit
4
6:5
7
Name
Asynchronous
Sample rate
Status valid
Access
RW
RW
RW
Description
Reflects the asx bit of the RATE (sampling rate) field of the audio
control packet.
Reports the X1 and X0 bits of the sample rate code from the RATE
field of the audio control packet.
Set to 1b when the audio control packet is present in the video
stream.
Error Status Register
3:0
Error counter
RW
Counts up to 15 errors since last reset.
Write 1b to any bit of this field to reset the entire counter to zero.
Indicates that an error has been detected in the ancillary packet
4
Ancillary CS fail
RW
checksum. This bit stays set until cleared by writing 1b to this
register.
Indicates that an error has been detected in at least one of the parity
5
Ancillary parity fail
RW
fields: the ancillary packet parity bit, the audio sample parity bit (for
SD-SDI) or the AES sample parity bit (for HD-SDI). This bit stays set
until cleared by writing 1b to this register.
6
Channel status CRC fail
RW
Indicates that an error has been detected in the channel status CRC.
This bit stays set until cleared by writing 1b to this register.
Indicates that an error has been detected in the ECRC that forms part
7
Audio packet ECRC fail
RW
of the HD audio data packet. This bit stays set until cleared by writing
1b to this register.
FIFO Status Register
Reports the amount of data in either the audio output FIFO or the
6:0
FIFO fill level
RO
Avalon-ST audio FIFO when the optional Avalon-ST Audio interface is
used.
This register bit goes high if there is either underflow/overflow of the
audio output FIFO or the overflow of the Avalon-ST audio FIFO,
7
Overflow/Underflow
RW
depending on the output mode used. This register always goes high
at the beginning, so you must clear the audio FIFO first for the
register to indicate underflow or overflow.
Clock Status Register
4:0
6:5
Offset
Unused
RO
—
Returns the current status of the digital PLL used to create the output
64 × sample rate clock.
Reserved for future use.
To create a 48-kHz signal synchronous to the video clock, you must
7
74.17-MHz video clock
RO
detect whether a 1 or 1/1.001 video clock rate is used. If you detect a
1/1.001 video clock rate, this field returns high.
Channel Status RAM
Read accesses within the address range 10h to 3Fh to the channel
7:0
Channel status data
WO
status RAM. This field returns the 24 bytes of channel status for X
channel starting at address 10h and the 24 bytes of channel status for
Y channel starting at address 28h.
For register interface signals, refer to Table 4–7 on page 4–7 . All SDI audio cores use
the same register interface signals.
Serial Digital Interface (SDI) MegaCore Function
User Guide
February 2013 Altera Corporation
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