参数资料
| 型号： | IP-SDI |
| 厂商： | Altera |
| 文件页数： | 85/140页 |
| 文件大小： | 0K |
| 描述： | IP VIDEO INTERFACE - SDI |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | 视频系统用串行数字接口 |
| 许可证： | 初始许可证 |
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Chapter 3: Functional Description
Signals
Table 3–19. Transceiver Dynamic Reconfiguration Signals (Part 2 of 2)
3–55
Signal
PLL_SCANCLK
PLL_SCANCLKENA
PLL_SCANDATA
Direction
Input
Input
Input
Description
Drives the scanclk signal on the transceiver PLL to be
reconfigured.
Acts as a clock enable for the scanclk signal on the transceiver
PLL to be reconfigured.
Drives the scandata signal on the transceiver PLL to be
reconfigured. This signal holds the scan data input to the
transceiver PLL for the dynamically reconfigurable bits.
PLL_SCANDATAOUT
Output
Output
Determines when the transceiver PLL is reconfigured.
This signal holds the transceiver PLL scan data output from the
dynamically reconfigurable bits.
(1) These signals must be connected directly to a reconfiguration megafunction.
(2) The transceivers are available for Arria GX, Arria II GX, Arria V, Cyclone IV GX, Cyclone V, Hardcopy IV GX, Stratix II GX, Stratix IV, and Stratix V
devices only.
(3) SDI transmitters do not require the use of transceiver dynamic reconfiguration but to enable the cores to merge into a transceiver quad that has
transceiver dynamic reconfiguration enabled, you must connect these ports correctly.
(4) In the Quartus II software version 8.1 and later, the Stratix IV transceivers requires receiver buffer calibration through an ALTGX_RECONFIG
(transceiver dynamic reconfiguration) controller. The additional RECONFIG port bits are used for receiver buffer calibration. You must connect
these ports to the ALTGX_RECONFIG controller externally. For further information on the receiver buffer calibration, refer to the Stratix IV
Dynamic Reconfiguration chapter in volume 2 of the Stratix IV Device Handbook . If you are using the Quartus II software version 10.1, make
sure to upgrade the SDI MegaCore function to version 10.1 as well.
(5) N represents the number of channels instantiated.
(6) The SDI_GXB_POWERDOWN signal of all the instances that are to be combined in a single transceiver block must be connected to a single point
(same input or same logic). Any difference in the driving logic prevents the instances from being combined in a single transceiver block.
(7) This signal must be connected directly to the ALTPLL_RECONFIG megafunction, and only exposed to the top level when you select the Use PLL
reconfiguration for transceiver dynamic reconfiguration option in the SDI parameter editor.
(8) The transceivers are available for Cyclone IV GX devices only.
(9) You require rx_std and sdi_start_reconfig signals for PLL reconfiguration.
February 2013
Altera Corporation
Serial Digital Interface (SDI) MegaCore Function
User Guide
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| IP-SDI-II | 功能描述:开发软件 SDI II Video MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-SDRAM/DDR | 功能描述:开发软件 DDR SDRAM Control MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-SDRAM/DDR2 | 功能描述:开发软件 DDR2 SDRAM Control MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-SDRAM/DDR3 | 功能描述:开发软件 DDR3 SDRAM Control MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-SDRAM/HPDDR | 功能描述:开发软件 DDR SDRAM Control MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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