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参数资料
型号： IP-SDI
厂商： Altera
文件页数： 23/140页
文件大小： 0K
描述： IP VIDEO INTERFACE - SDI
标准包装： 1
系列： *
类型： MegaCore
功能： 视频系统用串行数字接口
许可证： 初始许可证
Chapter 2: Getting Started
2–9
Simulating the Design
A testbench basically consists of transmit test and receive test. The transmit test
accepts the same serial data as the receive device under test (DUT), deserializes and
decodes the transmitted data, and computes the number of time reference signals
(TRS) seen. The receive test verifies the features that are supported by the SDI receiver
by monitoring the received data, status bits, line numbering and other related
features.
For dual and triple standard modes, the SDI receiver requires reconfiguration. The
SDI receiver reconfigures using transceiver dynamic reconfiguration to perform
autodetection and locking to different SDI video standards. For more details about
transceiver dynamic reconfiguration, refer to “Transceiver Dynamic Reconfiguration
for Dual Standard and Triple Standard Receivers” on page 3–27 .
Simulate with IP Functional Simulation Models
You can simulate your design using the MegaWizard-generated VHDL and Verilog
HDL IP functional simulation models.
You can use the IP functional simulation model with any Altera-supported VHDL or
Verilog HDL simulator.
To use the IP functional simulation model that you created in “Setting Up Simulation”
on page 2–6 , create a suitable testbench.
f For more information about IP functional simulation models, refer to the Simulating
Altera Designs chapter in volume 3 of the Quartus II Handbook .
Simulating with the ModelSim Simulator
For Arria and Stratix series of devices, Altera provides two fixed testbenches as
examples in the simulation\modelsim < video standard > \modelsim directory, where
< video standard > is hdsdi or hdsdi_dual_link . The testbenches instantiate the design
and test the HD-SDI or dual link mode of operation. To use one of these testbenches
with the ModelSim ? -Altera simulator, follow these steps:
1. In a text editor, open the simulation batch file, simulation\modelsim < video
standard > \modelsim\sdi_sim.bat . Edit it to point to your installation of the
ModelSim-Altera simulator and the Quartus II software, and edit the path:
set PATH = %MODELSIM_DIR%\win32aloem
set QUARTUS_ROOTDIR=c:\altera\81\quartus
For example, edit QUARTUS_ROOTDIR=/tools/acds/11.0/157/linux32/quartus .
1
Where < video standard > is hdsdi or hdsdi_dual_link .
2. Start the ModelSim-Altera simulator.
3. Run sdi_sim.bat in the simulation\modelsim < video standard > \modelsim
directory. This file compiles the design and starts the ModelSim-Altera simulator.
A selection of signals appears on the waveform viewer. The simulation runs
automatically, providing a pass/fail indication on completion.
February 2013
Altera Corporation
Serial Digital Interface (SDI) MegaCore Function
User Guide
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IP-SDI-II 功能描述:开发软件 SDI II Video MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IP-SDRAM/DDR 功能描述:开发软件 DDR SDRAM Control MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IP-SDRAM/DDR2 功能描述:开发软件 DDR2 SDRAM Control MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IP-SDRAM/DDR3 功能描述:开发软件 DDR3 SDRAM Control MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IP-SDRAM/HPDDR 功能描述:开发软件 DDR SDRAM Control MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
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