参数资料
型号: IP-SDI
厂商: Altera
文件页数: 94/140页
文件大小: 0K
描述: IP VIDEO INTERFACE - SDI
标准包装: 1
系列: *
类型: MegaCore
功能: 视频系统用串行数字接口
许可证: 初始许可证
4–6
Chapter 4: SDI Audio IP Cores
SDI Audio Embed MegaCore Function
Table 4–5 lists the Avalon-ST audio signals when you instantiate the SDI Audio
Embed MegaCore function in SOPC Builder.
Table 4–5. Avalon-ST Audio Signals for SDI Audio Embed MegaCore Function
Signal
aud( n) _clk
aud( n) _ready
aud( n) _valid
Width
[0:0]
[0:0]
[0:0]
Direction
Input
Output
Input
Description
Clocked audio clock. All the audio input signals are
synchronous to this clock.
Avalon-ST ready signal. Assert this signal when the
device is able to receive data.
Avalon-ST valid signal. The MegaCore function
asserts this signal when it receives data.
Avalon-ST start of packet signal. The MegaCore
aud( n) _sop
[0:0]
Input
function asserts this signal when it is starting a new
frame.
aud( n) _eop
aud( n) _channel
aud( n) _data
[0:0]
[7:0]
[23:0]
Input
Input
Input
Avalon-ST end of packet signal. The MegaCore
function asserts this signal when it is ending a frame.
Avalon-ST select signal. Use this signal to select a
specific channel.
Avalon-ST data bus. This bus transfers data.
Note to Table 4–5 :
(1) (n) represents the channel number.
Table 4–6 lists the direct control interface signals. These signals are exposed as ports if
you turn off the Include Avalon-MM Control Interface parameter.
Table 4–6. Direct Control Interface Signals (Part 1 of 2)
Signal
reg_clk
audio_control
extended_control
video_status
audio_status
cs_control
sine_freq_ch1
sine_freq_ch2
sine_freq_ch3
sine_freq_ch4
csram_addr
Width
[0:0]
[7:0]
[7:0]
[7:0]
[7:0]
[15:0]
[7:0]
[7:0]
[7:0]
[7:0]
[5:0]
Direction
Input
Input
Input
Output
Output
Input
Input
Input
Input
Input
Input
Description
Clock for the direct control interface.
This signal does the same function as the audio control
register in Table 4–9 .
This signal does the same function as the extended control
register in Table 4–9 .
This signal does the same function as the video status
register in Table 4–9 .
This signal does the same function as the audio status
register in Table 4–9 .
This signal does the same function as the channel status
control registers in Table 4–9 .
This signal does the same function as the sine channel 1
frequency register in Table 4–9 .
This signal does the same function as the sine channel 2
frequency register in Table 4–9 .
This signal does the same function as the sine channel 3
frequency register in Table 4–9 .
This signal does the same function as the sine channel 4
frequency register in Table 4–9 .
Channel status RAM address.
Serial Digital Interface (SDI) MegaCore Function
User Guide
February 2013 Altera Corporation
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