参数资料
| 型号： | IP-SDI |
| 厂商： | Altera |
| 文件页数： | 55/140页 |
| 文件大小： | 0K |
| 描述： | IP VIDEO INTERFACE - SDI |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | 视频系统用串行数字接口 |
| 许可证： | 初始许可证 |
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Chapter 3: Functional Description
3–25
Block Description
First, the transceiver controller makes a coarse rate detection of the incoming data
stream. Then, the transceiver is reprogrammed using transceiver dynamic
the correct rate for the standard that has been detected. After the reprogramming, the
transceiver attempts to lock to the incoming stream. If no valid data is seen in 0.1 s, the
receiver path is reset and the rate detection is performed again.
At the start of the rate detection process, the level of the three enable_xx signals is
sampled. The level of these signals and the knowledge of the currently programmed
state of the transceiver determines if the transceiver requires programming. This
process ensures that the transceiver is reprogrammed only when necessary.
Locking to the Incoming SDI Stream
The transceiver control state machine uses the presence (or absence) of TRSs on the
stream to determine if SDI is being correctly received. A single, valid TRS indicates to
the control state machine that the receiver is acquiring some valid SDI samples. The
control state machine only deasserts this flag when it does not detect any EAV
sequences within the number of consecutive lines you specified. At this point, the
controller state machine resets and performs the relock algorithm, refer to
Figure 3–14. Locking Algorithm
trs_strobe
n-th missing EAV New TRS reasserts
word count
trs_loose_lock
Because the aligner realigns to a new alignment if two consecutive TRSs with the
same alignment are detected, this scheme allows for an SDI source switch and an
alignment change without affecting the transceiver reset state machine.
The SDI MegaCore function also monitors the incoming EAV and SAV signals to
ensure their spacing is consistent over a number of lines. The MegaCore function
monitors by incrementing a counter on each incoming SDI word and storing the count
values at which an EAV or SAV is detected. If the EAV and SAV spacing is consistent
over 6 video lines, the MegaCore function indicates trs_locked on the rx_status[3]
output.
An enhancement in the current SDI MegaCore function allows a number of missing
EAV or SAV that you specify to be tolerated without deasserting the trs_locked
signal.
For example, when you specify the Tolerance to consecutive missed EAV/SAV
parameter to 2 , one or two consecutive missing EAVs set a “missed” flag but do not
cause the trs_locked signal to deassert. A good EAV in the correct position resets the
“missed” flag.
February 2013
Altera Corporation
Serial Digital Interface (SDI) MegaCore Function
User Guide
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| IP-SDI-II | 功能描述:开发软件 SDI II Video MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-SDRAM/DDR | 功能描述:开发软件 DDR SDRAM Control MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-SDRAM/DDR2 | 功能描述:开发软件 DDR2 SDRAM Control MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-SDRAM/DDR3 | 功能描述:开发软件 DDR3 SDRAM Control MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-SDRAM/HPDDR | 功能描述:开发软件 DDR SDRAM Control MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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