- 您现在的位置：买卖IC网 > PDF目录98071 > S5933QE (APPLIEDMICRO INC) PCI BUS CONTROLLER, PQFP160 PDF资料下载
参数资料
| 型号： | S5933QE |
| 厂商： | APPLIEDMICRO INC |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封装： | PLASTIC, QFP-160 |
| 文件页数： | 104/176页 |
| 文件大小： | 823K |
| 代理商： | S5933QE |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页当前第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页第165页第166页第167页第168页第169页第170页第171页第172页第173页第174页第175页第176页
3-41
PCI CONFIGURATION REGISTERS
S5933
Table 22a. Base Address Register — Memory (Bit 0 = 0)
31:4
Base Address Location. These bits are used to position the decoded region in memory space. Only
bits which return a 1 after being written as 1 are usable for this purpose. Except for Base Address
Register 0, these bits are individually enabled by the contents sourced from the external boot memory.
3
Prefetchable. When set as a 1, this bit signifies that this region of memory can be cached. Cachable
regions can only be located within the region altered through PCI bus memory writes. This bit, when
set, also implies that all read operations will return the data associated for all bytes regardless of the
Byte Enables. Memory space which cannot support this behavior should leave this bit in the zero
state. For Base Addresses 1 through 4, this bit is set by the Reset pin and later initialized by the
external boot memory (if present). Base Address Register 0 always has this bit set to 0. This bit is read
only from the PCI interface.
2:1
Memory Type. These two bits identify whether the memory space is 32 or 64 bits wide and if the space
location is restricted to be within the first megabyte of memory space. The table below describes the
encoding:
Bits
Description
2 1
0 0
Region is 32 bits wide and can be located anywhere in 32 bit memory space.
0 1
Region is 32 bits wide and must be mapped below the first MByte of memory space.
1 0
Region is 64 bits wide and can be mapped anywhere within 64 bit memory space.
(Not supported by this controller.)
1 1
Reserved. (Not supported by this controller.)
1
The 64-bit memory space is not supported by this controller, so bit 2 should not be set. The only
meaningful option is whether it is desired to position memory space anywhere within 32-bit memory
space or restrain it to the first megabyte. For Base Addresses 1 through 5, this bit is set by the reset
pin and later initialized by the external boot memory (if present).
0
Space Indicator = 0. When set to 0, this bit identifies a base address region as a memory space and
the remaining bits in the base address register are defined as shown in Table 22a.
Bit
Description
Table 22b. Base Address Register — I/O (Bit 0 = 1)
Bit
Description
31:2
Base Address Location. These bits are used to position the decoded region in I/O space. Only bits
which return a “1” after being written as “1” are usable for this purpose. Except for Base Address 0,
these bits are individually enabled by the contents sourced from the external boot memory (EPROM
or nvRAM).
1
Reserved. This bit should be zero. (Note: disabled Base Address Registers will return all zeros for the
entire register location, bits 31 through 0).
0
Space Indicator = 1. When one this bit identifies a base address region as an I/O space and the
remaining bits in the base address register have the definition as shown in Table 11b.
相关PDF资料 |
PDF描述 |
|---|---|
| S6A0032 | 16 X 80 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC138 |
| S6A0069 | 16 X 40 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC80 |
| S6A0078 | 34 X 120 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC183 |
| S80296SA40 | 16-BIT, 40 MHz, MICROCONTROLLER, PQFP100 |
| S80486-DX4-75-S-V-8-B | 32-BIT, 75 MHz, MICROPROCESSOR, PQFP208 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| S5935 | 制造商:AMCC 制造商全称:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935_07 | 制造商:AMCC 制造商全称:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S59355QRC | 制造商:AppliedMicro 功能描述: |
| S5935QF | 制造商:AMCC 制造商全称:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935QRC | 制造商:AppliedMicro 功能描述:PCI Master Device 160-Pin PQFP |
发布紧急采购，3分钟左右您将得到回复。