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参数资料
型号： S5933QE
厂商： APPLIEDMICRO INC
元件分类： 总线控制器
英文描述： PCI BUS CONTROLLER, PQFP160
封装： PLASTIC, QFP-160
文件页数： 7/176页
文件大小： 823K
代理商： S5933QE
3-116
MAILBOX OVERVIEW
S5933
Mailbox Empty/Full Conditions
The PCI and Add-On interfaces each have a mailbox
status register. The PCI Mailbox Empty/Full Status
(MBEF) and Add-On Mailbox Empty/Full Status
(AMBEF) Registers indicate the status of all bytes
within the mailbox registers. A write to an outgoing
mailbox sets the status bits for that mailbox. The byte
enables determine which bytes within the mailbox be-
come full (and which status bits are set).
An outgoing mailbox for one interface is an incoming
mailbox for the other. Therefore, incoming mailbox
status bits on one interface are identical to the corre-
sponding outgoing mailbox status bits on the other
interface. The following list shows the relationship be-
tween the mailbox registers on the PCI and Add-On
interfaces.
PCI Interface
Add-On Interface
Outgoing Mailbox 1
= Incoming Mailbox 1
Outgoing Mailbox 2
= Incoming Mailbox 2
Outgoing Mailbox 3
= Incoming Mailbox 3
Outgoing Mailbox 4
= Incoming Mailbox 4
Incoming Mailbox 1
= Outgoing Mailbox 1
Incoming Mailbox 2
= Outgoing Mailbox 2
Incoming Mailbox 3
= Outgoing Mailbox 3
Incoming Mailbox 4
= Outgoing Mailbox 4
PCI Mailbox Empty/Full = Add-On Mailbox Empty/
Full
A write to an outgoing mailbox also writes data into
the incoming mailbox on the other interface. It also
sets the status bits for the outgoing mailbox and the
status bits for the incoming mailbox on the other in-
terface. Reading the incoming mailbox clears all cor-
responding status bits in the Add-On and PCI
mailbox status registers (AMBEF and MBEF).
For example, a PCI write is performed to the PCI out-
going mailbox 2, writing bytes 0 and 1 (BE0# and
BE1# asserted). Reading the PCI Mailbox Empty/Full
Status Register (MBEF) indicates that bits 4 and 5 are
set. These bits indicate that outgoing mailbox 2, bytes
0 and 1 are full. Reading the Add-On Mailbox Empty/
Full Status Register (AMBEF) shows that bits 4 and 5
in this register are also set, indicating Add-On incom-
ing mailbox 2, bytes 0 and 1 are full. An Add-On read
of incoming mailbox 2, bytes 0 and 1 clears the status
bits in both the MBEF and AMBEF status registers.
To reset individual flags in the MBEF and AMBEF
registers, the corresponding byte must be read from
the incoming mailbox. The PCI and Add-On mailbox
status registers, MBEF and AMBEF, are read-only.
Mailbox flags may be globally reset from either the
PCI interface or the Add-On interface. The PCI Bus
Master Control/Status Register (MCSR) and the Add-
On General Control/Status Register (AGCSTS) each
have a bit to reset all of the mailbox status flags.
Mailbox Interrupts
The designer has the option to generate interrupts to
the PCI and Add-On interfaces when specific mailbox
events occur. The PCI and Add-On interfaces can
each define two conditions where interrupts may be
generated. An interrupt can be generated when an
incoming mailbox becomes full and/or when an outgo-
ing mailbox becomes empty. A specific byte within a
specific mailbox is selected to generate the interrupt.
The conditions defined to generate interrupts to the
PCI interface do not have to be the same as the condi-
tions defined for the Add-On interface. Interrupts are
cleared through software.
For incoming mailbox interrupts, when the specified
byte becomes full, an interrupt is generated. The in-
terrupt might be used to indicate command or status
information has been provided, and must be read.
For PCI incoming mailbox interrupts, the S5933 as-
serts the PCI interrupt, INTA#. For Add-On incoming
mailbox interrupts, the S5933 asserts the Add-On in-
terrupt, IRQ#.
For outgoing mailbox interrupts, when the specified
byte becomes empty, an interrupt is generated. The
interrupt might be used to indicate that the other in-
terface has received the last information sent and
more may be written. For PCI outgoing mailbox inter-
rupts, the S5933 asserts the PCI interrupt, INTA#.
For Add-On outgoing mailbox interrupts, the S5933
asserts the Add-On interrupt, IRQ#.
Add-On Outgoing Mailbox 4, Byte 3 Access
PCI incoming mailbox 4, byte 3 (Add-On outgoing
mailbox 4, byte 3) does not function exactly like the
other mailbox bytes. When an a serial nv memory
boot device or no external boot device is used, the
S5933 pins EA7:0 are redefined to provide direct ex-
ternal access to Add-On outgoing mailbox 4, byte 3.
EA8 is redefined to provide a load clock which may
be used to generate a PCI interrupt. The pins are
redefined as follows:
Signal Pin
Add-On Outgoing Mailbox
EA0/EMB0
Mailbox 4, bit 24
EA1/EMB1
Mailbox 4, bit 25
EA2/EMB2
Mailbox 4, bit 26
EA3/EMB3
Mailbox 4, bit 27
EA4/EMB4
Mailbox 4, bit 28
EA5/EMB5
Mailbox 4, bit 29
EA6/EMB6
Mailbox 4, bit 30
EA7/EMB7
Mailbox 4, bit 31
EA8/EMBCLK Mailbox 4, byte 3 load clock
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